JPH031446U

JPH031446U -

Info

Publication number: JPH031446U
Application number: JP5868689U
Authority: JP
Priority date: 1989-05-23
Filing date: 1989-05-23
Publication date: 1991-01-09
Anticipated expiration: 2004-05-23
Also published as: JPH0713227Y2

Description

[Brief explanation of drawings]

第１ａ図は、本考案の一実施例に係る半導体集
積回路用リードフレームを構成する第１の金属板
状形成体の平面図である。第１ｂ図は、第１ａ図
に示す第１の金属板状形成体のＡ−Ａ断面図であ
る。第１ｃ図は、本考案の一実施例に係る半導体
集積回路用リードフレームを構成する第２の金属
板状形成体の平面図である。第１ｄ図は、第１ｃ
図に示す第２の金属板状形成体のＢ−Ｂ断面図で
ある。第１ｅ図は、本考案の一実施例に係る半導
体集積回路用リードフレームの平面図である。第
１ｆ図は、第１ｅ図に示す半導体集積回路用リー
ドフレームのＤ−Ｄ断面図である。第１ｇ図は、
第１ａ図に１点鎖線をもつて囲まれた領域２の概
念的拡大図である。第１ｈ図は第１ｇ図のＥ−Ｅ
断面図である。第１ｉ図は、第１ｃ図に１点鎖線
をもつて囲まれた領域３の概念的拡大図である。
第１ｊ図は第１ｉ図のＦ−Ｆ断面図である。第１
ｋ図は、第１ｅ図に１点鎖線をもつて囲まれた領
域４の概念的拡大図である。第１ｌ図は第１ｋ図
のＧ−Ｇ断面図である。第２図は、従来技術に係
る半導体集積回路用リードフレームの平面図であ
る。第３図は、従来技術に係る半導体集積回路パ
ツケージの斜視図である。第４図は、従来技術に
係るウエツトエツチング法を使用して製造された
インナーリードの断面図である。第５図は、従来
技術に係るプレス打抜き法を使用して製造された
インナーリードの断面図である。１……半導体集積回路用リードフレーム、２…
…第１の金属板状成形体の平面図の一部領域であ
る。３……第２の金属板状成形体の平面図の一部
領域である。４……本考案の一実施例に係る半導
体集積回路用リードフレームの一部領域である。
９……ウエツトエツチング法を使用して製造した
リード、９１……突起、１０……プレス打抜き法
を使用して製造したリード、１１……半導体集積
回路チツプ支持台、１２……半導体集積回路チツ
プ、１３……半導体集積回路のボンデイングパツ
ド、１４……プラスチツク材よりなる被覆材、１
５……半導体集積回路チツプ支持台支持バー、１
６……保持バー、１６１，１６５……他の部材と
同一の平面をなす面、１６２，１６６……保持バ
ーの相互に対接する面、１６３，１６４……厚さ
が減縮されている保持バー、１７……第１の金属
板状成形体、１８……第２の金属板状成形体。 FIG. 1a is a plan view of a first metal plate-shaped body constituting a lead frame for a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 1b is a sectional view taken along the line AA of the first metal plate-like formation shown in FIG. 1a. FIG. 1c is a plan view of a second metal plate-shaped body constituting a lead frame for a semiconductor integrated circuit according to an embodiment of the present invention. Figure 1d is the same as Figure 1c.
It is a BB sectional view of the 2nd metal plate-like formation body shown in a figure. FIG. 1e is a plan view of a lead frame for a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 1f is a sectional view taken along line DD of the lead frame for a semiconductor integrated circuit shown in FIG. 1e. Figure 1g is
FIG. 1a is a conceptual enlarged view of region 2 surrounded by a dash-dotted line in FIG. 1a. Figure 1h is E-E of Figure 1g.
FIG. FIG. 1i is a conceptual enlarged view of the region 3 surrounded by a dashed line in FIG. 1c.
FIG. 1j is a sectional view taken along line FF in FIG. 1i. 1st
FIG. 1E is a conceptual enlarged view of the region 4 surrounded by a dashed line in FIG. 1E. FIG. 11 is a sectional view taken along line GG in FIG. 1k. FIG. 2 is a plan view of a lead frame for a semiconductor integrated circuit according to the prior art. FIG. 3 is a perspective view of a semiconductor integrated circuit package according to the prior art. FIG. 4 is a cross-sectional view of an inner lead manufactured using a conventional wet etching method. FIG. 5 is a cross-sectional view of an inner lead manufactured using a press punching method according to the prior art. 1...Lead frame for semiconductor integrated circuit, 2...
... is a partial area of a plan view of the first metal plate-shaped molded body. 3... This is a partial area of a plan view of the second metal plate-shaped molded body. 4...This is a partial area of a lead frame for a semiconductor integrated circuit according to an embodiment of the present invention.
9...Lead manufactured using the wet etching method, 91...Protrusion, 10...Lead manufactured using the press punching method, 11...Semiconductor integrated circuit chip support, 12...Semiconductor integrated circuit Chip, 13... Bonding pad of semiconductor integrated circuit, 14... Covering material made of plastic material, 1
5... Semiconductor integrated circuit chip support stand support bar, 1
6... Holding bar, 161, 165... Surface forming the same plane as other members, 162, 166... Mutually opposing surfaces of the holding bar, 163, 164... Holding bar with reduced thickness. , 17...first metal plate-shaped molded body, 18...second metal plate-shaped molded body.

Claims

[Claims for Utility Model Registration] The semiconductor integrated circuit chip support 11, the semiconductor integrated circuit chip support support bar 15, alternately selected halves of the leads 9, and one surface 161 are the members 11, 15, 9. is the same as the surface of , but the other surface is 162
is one half of the holding bar whose thickness is reduced to approximately 1/2 of the thickness of the members 11, 15, and 9.
63; the remaining half of the leads 9; one surface 165 is the same as the surface of the leads 9; the other surface 166 has a reduced thickness and is similar to the The approximate thickness of lead 9 is 1/
2 and the other half 164 of the holding bar, the second metal plate-like molded body 18 and the first metal plate-like molded body 17. This is a lead frame for a semiconductor integrated circuit, characterized in that the two surfaces 162 and 166 having the reduced thickness are connected to each other.