JPH03142846A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH03142846A JPH03142846A JP1281425A JP28142589A JPH03142846A JP H03142846 A JPH03142846 A JP H03142846A JP 1281425 A JP1281425 A JP 1281425A JP 28142589 A JP28142589 A JP 28142589A JP H03142846 A JPH03142846 A JP H03142846A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- metallized
- semiconductor
- gold
- ceramic substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 73
- 239000000919 ceramic Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910000679 solder Inorganic materials 0.000 abstract description 14
- 238000000034 method Methods 0.000 abstract description 6
- 230000005496 eutectics Effects 0.000 abstract description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 4
- 239000010931 gold Substances 0.000 abstract description 4
- 229910052737 gold Inorganic materials 0.000 abstract description 4
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 abstract description 3
- 239000006023 eutectic alloy Substances 0.000 abstract description 3
- 239000011888 foil Substances 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 241000218202 Coptis Species 0.000 description 2
- 235000002991 Coptis groenlandica Nutrition 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、セラミックス基板を用いた半導体パッケージ
に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor package using a ceramic substrate.
（従来の技術）
半導体素子は、外部環境からの保護、取扱の容易さ等か
ら、セラミックス焼結体でなる基板に搭載され半導体パ
ッケージとして用いることが一般に行われている。半導
体パッケージは、半導体素子、これを搭載するセラミッ
クス基板及び半導体素子に電気信号を入出力する手段等
で構成される。このような半導体パッケージは、最近で
は、ＬＳＩチップ等の半導体素子の高集積化と高速化が
進んでいる。また、電子装置を小型で高機能にする目的
から実装の高密度化が進み、１チツプが有する機能数の
増加に伴って、それぞれの機能に対する入出力用のリー
ドピン数も増加している。(Prior Art) Semiconductor elements are generally mounted on a substrate made of a sintered ceramic body and used as a semiconductor package for reasons such as protection from the external environment and ease of handling. A semiconductor package is composed of a semiconductor element, a ceramic substrate on which the semiconductor element is mounted, a means for inputting and outputting electrical signals to and from the semiconductor element, and the like. Recently, in such semiconductor packages, semiconductor elements such as LSI chips are becoming more highly integrated and faster. Further, in order to make electronic devices compact and highly functional, the density of packaging is increasing, and as the number of functions one chip has increases, the number of input/output lead pins for each function is also increasing.
半導体素子は、セラミックス基板のほぼ中央部にダイボ
ンディングされるが、その位置は高い精度が要求される
。すなわち、半導体素子の入出力用端子はミボンディン
グワイヤによってセラミックス基板の表面に設けられた
導体部分に導電接続されるが、この接続は自動化された
ワイヤボンディング装置により行なわれるためセラミッ
クス基板の表面に設けられた導体部分との相対位置の正
確さが要求されるのである。上記のように、入出力用の
リードピン数が多い場合、ワイヤボンディング装置の位
置認識精度やボンディングワイヤの長さに制限があるた
めに半導体素子のダイボンディング位置の精度が特に重
要である。Semiconductor elements are die-bonded almost at the center of a ceramic substrate, but the positioning requires high precision. In other words, the input/output terminals of the semiconductor element are conductively connected to the conductor portions provided on the surface of the ceramic substrate using micro-bonding wires, but since this connection is made by automated wire bonding equipment, Therefore, accuracy of the relative position with respect to the conductor portion is required. As described above, when the number of input/output lead pins is large, the accuracy of the die bonding position of the semiconductor element is particularly important because there are limitations on the position recognition accuracy of the wire bonding device and the length of the bonding wire.
半導体素子のダイボンディングは、信頼性が要求される
場合等では半田付けによる接合が行われている。この場
合の半田付けには、金合金による共晶半田が多く用いら
れ、セラミックス基板と半導体素子との間にこの半田を
介在させて接合する。For die bonding of semiconductor elements, joining by soldering is performed when reliability is required. In this case, eutectic solder made of gold alloy is often used for soldering, and the ceramic substrate and the semiconductor element are bonded with this solder interposed between them.
これらの半田は、４００℃付近に加熱することにより溶
融するが、その際半田の粘度が低くなるため半導体素子
の位置がずれることがあり、このことを防止するための
手段が考えられている。例えば、個別に人手によるダイ
ボンディングをおこなうこと、治具を使用して半導体素
子を固定すること、あるいはセラミックス基板に半導体
素子を固定する突起をつけること等である。These solders are melted by heating to around 400° C., but at this time the viscosity of the solder decreases and the position of the semiconductor element may shift.Means have been devised to prevent this. For example, die bonding may be performed individually by hand, semiconductor elements may be fixed using a jig, or protrusions for fixing semiconductor elements may be provided on a ceramic substrate.
（発明が解決しようとする課題）
しかしながら、個別に人手によるダイボンディングをお
こなう方法では、接合位置の精度に限界があるとともに
高温での接合作業の安全性に問題があり、治具を使用し
て半導体素子を固定する方法では、製品ごとにそれぞれ
異なる治具が必要であるとともに作業が複雑になるとい
う問題がある。また、セラミックス基板に半導体素子を
固定する突起をつける方法では、セラミックス基板の突
起に必要な精度を得ることが難しいという問題がある。(Problem to be solved by the invention) However, with the method of individually performing die bonding manually, there is a limit to the accuracy of the bonding position and there are problems with the safety of bonding work at high temperatures. The method of fixing semiconductor elements has the problem that different jigs are required for each product and the work is complicated. Furthermore, in the method of attaching protrusions for fixing semiconductor elements to a ceramic substrate, there is a problem in that it is difficult to obtain the necessary precision for the protrusions on the ceramic substrate.
本発明は、このような問題に対処するためになされたも
ので、半導体素子が正確な位置に精度よくダイボンディ
ングされ、かつその位置は任意の位置に制御されてなる
、信頼性の高い半導体バ・ソケージを提供することを目
的とする。The present invention has been made to address such problems, and provides a highly reliable semiconductor board in which semiconductor elements are precisely die-bonded at precise positions and whose positions are controlled at arbitrary positions.・The purpose is to provide socage.
［発明の構成］
（課題を解決するための手段）
本発明の半導体パッケージは、セラミックス基板と、こ
のセラミックス基板上に搭載された半導体素子と、半導
体素子に電気的に接続されたリードピンとを有する半導
体パッケージであって、半導体素子の搭載部分のセラミ
ックス表面に半導体素子の位置決めのための非メタライ
ズ部分を設けてなることを特徴とするものである。[Structure of the Invention] (Means for Solving the Problems) A semiconductor package of the present invention includes a ceramic substrate, a semiconductor element mounted on the ceramic substrate, and lead pins electrically connected to the semiconductor element. This semiconductor package is characterized in that a non-metalized part for positioning the semiconductor element is provided on the ceramic surface of the part where the semiconductor element is mounted.
（作用）
本発明の半導体パッケージによれば、セラミックス表面
に設けるメタライズ領域を接合しようとする半導体素子
の大きさと等しくしその外側に非メタライズ部分を設け
ることにより、接合の際溶融する半田が前記のメタライ
ズ領域以外に流動することを阻止し半導体素子を精度よ
く所定の位置に接合することができる。すなわち、ダイ
ボンデインクに使用される金糸の共晶半田は、接合時に
メタライズされた領域以外には拡がらないため半田の溶
融による表面張力により半導体素子はメタライズされた
領域に自動的に位置決めされる。(Function) According to the semiconductor package of the present invention, the size of the metallized region provided on the ceramic surface is equal to the size of the semiconductor element to be bonded, and the non-metalized portion is provided outside of the metallized region, so that the solder that melts during bonding is It is possible to prevent the semiconductor element from flowing to areas other than the metallized area, and to bond the semiconductor element at a predetermined position with high precision. In other words, the gold thread eutectic solder used in die bonding does not spread beyond the metallized area during bonding, so the semiconductor element is automatically positioned in the metallized area due to the surface tension caused by the melting of the solder. .
したがって、特別の治具を用いることなく半導体素子の
正確な位置決めができるとともに、半田はメタライズ領
域内で均一に溶融して拡がり半田層の厚さが均一となる
ので安定した接合状態を得ることができる。なおセラミ
ックス表面に設けるメタライズ領域は、半導体素子に許
容される位置精度の範囲で設定することができる。また
、非メタライズ部分を段階的に設けておくことにより種
々の大きさの半導体素子の接合に対応することが可能で
ある。Therefore, it is possible to accurately position the semiconductor element without using a special jig, and the solder melts and spreads uniformly within the metallized area, making the thickness of the solder layer uniform, making it possible to obtain a stable bonding state. can. Note that the metallized region provided on the ceramic surface can be set within the range of positional accuracy allowed by the semiconductor element. Further, by providing the non-metalized portions in stages, it is possible to cope with the bonding of semiconductor elements of various sizes.
このように、半導体素子を精度よく所定の位置に接合す
ることにより、得られる半導体パッケージの信頼性を向
上させることができる。In this way, by accurately bonding semiconductor elements at predetermined positions, the reliability of the resulting semiconductor package can be improved.
（実施例） 以下、本発明の実施例について説明する。(Example) Examples of the present invention will be described below.
第１図に本発明の半導体パッケージに適用するセラミッ
クス基板の一例を示す。このセラミックス基板は例えば
窒化アルミニウムを主成分とし３層構造
のセラミックス３で形成されており、半導体素子を搭載
する中央部分の凹部に着目すると、この部分には半導体
素子を搭載するメタライズ領域１が設けられている。メ
タライズ領域１は搭載しようとする半導体素子の大きさ
に合致する正方形の面積を有する。そして、メタライズ
領域１の周囲には半導体素子の位置決めのための非メタ
ライズ部分（セラミックスの露出部分）２が設けられて
いる。また、メタライズ領域１の内部にも相似の正方形
を形づくるように非メタライズ部分２が設けられている
。これは大きさの異なる半導体素子の搭載に対応するた
めのものである。メタライズ領域１は、タングステンを
主成分とするメタライズペーストを塗布して熱処理を施
したものに、ニッケルめっき、金めつきを施して形成し
たものである。メタライズ領域１および非メタライズ部
分２の外側には、−段高くなった段部に導電端子部４が
設けられている。FIG. 1 shows an example of a ceramic substrate applied to the semiconductor package of the present invention. This ceramic substrate is made of ceramic 3 with a three-layer structure mainly composed of aluminum nitride, for example, and if we focus on the recessed part in the center where the semiconductor element is mounted, a metallized area 1 on which the semiconductor element is mounted is provided in this part. It is being The metallized region 1 has a square area that matches the size of the semiconductor element to be mounted. A non-metalized portion (exposed ceramic portion) 2 is provided around the metallized region 1 for positioning the semiconductor element. Furthermore, non-metalized portions 2 are provided inside the metalized region 1 so as to form similar squares. This is to accommodate mounting of semiconductor elements of different sizes. The metallized region 1 is formed by applying a metallizing paste containing tungsten as a main component and subjecting it to heat treatment, followed by nickel plating and gold plating. On the outside of the metallized region 1 and the non-metalized portion 2, a conductive terminal portion 4 is provided at a step portion that is higher than the other step.
第１図に示すセラミックス基板に半導体素子を接合する
。すなわち、セラミックス基板のメタライズ領域１に合
致し半導体素子と同一の大きさを有する金−ゲルマニウ
ム共晶合金箔を、メタライズ領域１に載置し、その上に
金メタライズされた裏面を有する半導体素子を重ね、非
酸化性雰囲気で約４００℃に加熱して接合するのである
。この際、金糸の共晶半田はメタライズ領域１以外には
拡がらないため半田の溶融による表面張力により半導体
素子はメタライズ領域１に正確に位置決めされる。A semiconductor element is bonded to the ceramic substrate shown in FIG. That is, a gold-germanium eutectic alloy foil that matches the metallized area 1 of the ceramic substrate and has the same size as the semiconductor element is placed on the metallized area 1, and a semiconductor element having a back surface metallized with gold is placed on top of the gold-germanium eutectic alloy foil. They are stacked and bonded by heating to about 400°C in a non-oxidizing atmosphere. At this time, since the eutectic solder of the gold thread does not spread beyond the metallized area 1, the semiconductor element is accurately positioned in the metallized area 1 due to the surface tension caused by the melting of the solder.
このようにして得られたものの断面を第２図に示す。第
２図に示すように半導体素子５は共晶半田６により所定
のメタライズ領域１に接合される。A cross section of the product thus obtained is shown in FIG. As shown in FIG. 2, the semiconductor element 5 is bonded to a predetermined metallized region 1 by eutectic solder 6. As shown in FIG.
半導体素子５は、ボンディングワイヤ７によりそれぞれ
の導電端子部４に導電接続される。上記のように半導体
素子５の位置がずれることなく正確に設定されるので、
自動機によるボンディング工程を支障なく行うことがで
きる。The semiconductor elements 5 are conductively connected to the respective conductive terminal portions 4 by bonding wires 7 . As described above, the position of the semiconductor element 5 is set accurately without shifting.
The bonding process using an automatic machine can be performed without any problems.
［発明の効果］
以上説明したように、本発明の半導体パッケージは、半
導体素子がダイボンディングされる位置の周囲に
非メタライズ部分が形成されているので、この非メタラ
イズ部分により半導体素子の接合位置が正確に位置決め
される。したがって以後の自動化されたボンディング工
程を支障なく行うことができる。また、半導体素子の接
合は特別の治具等を用いることなく容易に行うことがで
きるので作業効率が向上する。さらに、半導体素子とセ
ラミックス基板との接合強度が向上し信頼性の高い半導
体パッケージと擦ることができる。[Effects of the Invention] As explained above, in the semiconductor package of the present invention, the non-metalized portion is formed around the position where the semiconductor element is die-bonded, so the bonding position of the semiconductor element is determined by the non-metalized portion. accurately positioned. Therefore, the subsequent automated bonding process can be performed without any trouble. Furthermore, since semiconductor elements can be easily bonded without using special jigs or the like, work efficiency is improved. Furthermore, the bonding strength between the semiconductor element and the ceramic substrate is improved, and a highly reliable semiconductor package can be achieved.
第１図は本発明の一実施例の半導体パッケージを構成す
るセラミックス基板の平面図、第２図は本発明の一実施
例の半導体パッケージを断面で示す図面である。
１・・・・・・・・・メタライズ領域
２．２ａ・・・非メタライズ部分
３・・・・・・・・・セラミックス
４・・・・・・・・・導電端子部
５・・・・・・・・・半導体素子
６・・・・・・リードピンFIG. 1 is a plan view of a ceramic substrate constituting a semiconductor package according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of the semiconductor package according to an embodiment of the present invention. 1...Metallized area 2.2a...Non-metalized portion 3...Ceramics 4...Conductive terminal portion 5... ... Semiconductor element 6 ... Lead pin
Claims (1)
搭載された半導体素子と、半導体素子に電気的に接続さ
れたリードピンとを有する半導体パッケージであって、
半導体素子の搭載部分のセラミックス表面に半導体素子
の位置決めのための非メタライズ部分を設けてなること
を特徴とする半導体パッケージ。(1) A semiconductor package including a ceramic substrate, a semiconductor element mounted on the ceramic substrate, and lead pins electrically connected to the semiconductor element,
A semiconductor package characterized in that a non-metalized part for positioning the semiconductor element is provided on the ceramic surface of the part where the semiconductor element is mounted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1281425A JPH03142846A (en) | 1989-10-27 | 1989-10-27 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1281425A JPH03142846A (en) | 1989-10-27 | 1989-10-27 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03142846A true JPH03142846A (en) | 1991-06-18 |
Family
ID=17638985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1281425A Pending JPH03142846A (en) | 1989-10-27 | 1989-10-27 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03142846A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014132682A (en) * | 2014-03-14 | 2014-07-17 | Renesas Electronics Corp | Resin encapsulated semiconductor device manufacturing method |
-
1989
- 1989-10-27 JP JP1281425A patent/JPH03142846A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014132682A (en) * | 2014-03-14 | 2014-07-17 | Renesas Electronics Corp | Resin encapsulated semiconductor device manufacturing method |
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