JPH03142542A - Address generating device for microprocessor - Google Patents

Abstract

PURPOSE:To produce an address having the narrow bit width by producing again a physical address to use a produced address as an address of a lap- around destination as long as the produced address should be lapped around. CONSTITUTION:A 32-bit adder 1 outputs a 32-bit physical address, and the output side of the adder 1 is connected to a main storage 3. At the same time, the input side of the adder 1 is connected to a register file 6 via two 32-bit address buses 4 and 5. The file 6 outputs the address generating elements in both 32-bit and 16-bit widths. The bus 4 is used exclusively for transfer of the address elements of 32-bit width, and the bus 5 is used for transfer of the address elements of both 32-bit and 16-bit widths respectively. The bus 5 is also connected to the input side of a 16-bit address comparator 7. The comparator 7 compares the address value transferred in the 16-bit width with the prescribed value and decides whether the produced physical address should be corrected or not for lap-around.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an address generation device for an integrated circuit microprocessor, and more particularly to a method for generating a wraparound address space in which the minimum address is located directly above the maximum address. The present invention relates to an address generation device for.

BACKGROUND OF THE INVENTION An integrated circuit microprocessor has an address output for specifying the address of a main memory device connected via an address bus, and this address output is generated by an address generation device within the microprocessor. generated.

Here, in order to have a larger capacity memory, the number of bits of address output, and therefore the number of bits of the address generation device, is increasing year by year, from 8 bits to 16 bits, and from 16 bits to 32 bits. ing. but,
In order to maintain compatibility with conventional models, it is necessary to maintain the ability to calculate addresses in the narrow bit width of conventional models.

In order to meet such demands, in the past, the address generation device side was left as is, and the address elements with a narrow bit width for conventional models were arithmetically expanded to adapt to the address generation device with a wide bit width. I'm letting you do it. Using this method, it is possible to run many programs for conventional models with narrow bit widths.

In some conventional models with narrow bit widths, the address space is not a linear address space, but a so-called wrap-around address space where the largest address is located directly below the smallest address. You may have. This type of address space has a narrow bit width, and is therefore an effective way to use memory in models that have a small address space. Therefore, it is often used in important programs that make maximum use of the address capability of that model. However, such a wraparound address space cannot be created by simply expanding the address calculation width to match the address width of the higher-level device as described above.

Conventionally, in order to generate such a wraparound address space, hardware is connected outside the microprocessor to generate a pseudo wraparound address space.

(Problem to be Solved by the Invention) However, when generating a wraparound address space using an external circuit, only a specific address boundary, such as the maximum physical address of conventional models with a narrow bit width, can be generated. There was a problem that address wraparound could not be performed. That is, it is not possible to perform address wrap-around operations on finer structures of main memory such as byte boundaries, word boundaries, or baragraph boundaries.

In view of these points, it is an object of the present invention to wrap around Aviles in fine structures such as byte boundaries, word boundaries, or paragraph boundaries in an address space generated by an address generation element with a narrow bit width. In order to realize an address generation device that has become possible, it is now possible to generate addresses with a narrow bit width using an address generation device with a large bit width, which was previously impossible to perform as a complete substitute due to bit width incompatibility. be.

(Means for Solving the Problems) In order to solve the above problems, the present invention generates an address space that has at least a part of a specific area wrapped around so that the maximum address is located directly below the minimum address. In a microprocessor address generation device, based on at least one address generation element,
Physical address generation means for generating a physical address, address calculation width specification means for specifying an address calculation width, and when the address calculation width on the side with a smaller number of bits is specified by the address calculation width specification means, the physical determining means for determining whether the physical address generated by the address generating means is an address to be wrapped around in the specific area; and the physical address generated by the determining means is an address to be wrapped around. If it is determined that this is the case, the present invention is characterized by comprising a conversion means for converting the generated physical address into a wraparound destination address.

(Example) The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows the main structure of an address generation device according to a first embodiment of the present invention. The device of this example is capable of generating 32-bit and 16-bit wide addresses. In the figure, ■ is a 32-bit adder as address generation means, which outputs a 32-bit physical address. The output side of this adder is connected to a main memory 3 via an address bus 2. On the other hand, the input side of the adder 10 is
It is connected to the register file 6 via two 32-bit address buses 4.5. Address generation elements are output from the register file 6 in widths of 32 bits and 16 bits. One of the address buses 4 mentioned above is used only for transferring address elements with a width of 32 bits, and the other address bus 5 is used for transferring address elements with a width of 32 bits and 16 bits. The bus 5 on the latter side is also connected to the input side of a 16-bit address comparator 7. The comparator 7 compares the address value transferred in 16-bit width with a preset value to determine whether or not it is necessary to modify the generated physical address for wraparound.

Reference numeral 8 denotes a control logic circuit, which generates control signals in accordance with instructions supplied thereto to control the above-mentioned adders and comparators and input/output of data to and from the register file. Regarding the control related to the present invention, the register
Instruct file 6 whether to transfer address generation elements in 32-bit or 16-bit width, and
When transferring an address generation element with a width of 6 bits, a comparison permission signal is outputted to the comparator 7 to cause the comparator 7 to perform a comparison operation. Furthermore, if it is necessary to modify the generated physical address to cause it to wrap around, each element is driven and controlled to regenerate the physical address using address constants in the register file.

Here, the program stored in main memory is
It consists of a code area where instructions are defined, a data area where variables are defined, and a stack area. these are,
Addressed by segmentation addressing method.

In other words, these areas, segments, are treated independently from each other, and the location of specific data within each segment is determined by an address representing the location of each segment in memory space, and an address representing the location of the data within the segment. identified by the address. The address (segment value) representing the location of the segment in the above memory space is stored in the segment register 61 formed in the register file.
The addresses (offset values) representing specific data locations within each segment are calculated and specified by pointers within general purpose registers 62 within the register file.

A case will be described in which a program using 16-bit width addressing is run in the device of this example having this configuration. Here, the 16-bit memory space is addressed by segmentation.
It is assumed that the shaded segment in FIG. 2 is a wrap-around memory area in which the minimum address X (MIN) that also defines this area is located directly above the maximum address X (MAX) that also defines this area.

In this case, first, the control logic circuit 8 instructs to output an address generation element with a width of 16 bits. As a result, the register file 6 outputs an address generation element that specifies a segment value via the address bus 4, and the address generation element that specifies an offset value with a width of 16 bits is output from the other address bus 5. be done.

These address generation elements are added in a 32-bit adder l to generate a 32-bit physical address.

At the same time, the 16-bit wide address generation element
It is also supplied to a 6-bit address comparator 7. This comparator 7 is set to a comparison enabled state by the control logic circuit 8 when outputting an address generation element with a width of 16 bits.

Therefore, in this comparator, this address generating element is compared with a preset value. This value is the address value that should cause a wraparound operation, and if the 16-bit width address generation element (offset value) is smaller than this value, the control logic circuit 8 performs a 32-bit addition based on the comparison result. A control signal is output to the device 1 to cause the physical address calculated here to be output to the address bus 2.

However, when these two values become equal,
The comparison result of the comparator 7 is supplied to the control logic circuit 8 as a wraparound command. Upon receiving this signal, the control logic circuit 8 generates a physical address again using the wraparound address constant, so that the generated physical address becomes the wraparound destination address. do. Addressing of the wrap-around segment shown in FIG. 2 is performed using the address thus output.

First summer implementation group Next, FIG. 3 shows a configuration in which an additional circuit for wraparound is added to the 32-bit adder 1 described above. 32
The bit adder 1 includes a 1-bit arithmetic unit 11 and a carry arithmetic unit 12 for each of 32 bits. The l-bit arithmetic unit 12 has three inputs and one output.

The input is human power A from bus 4, which is the first addition element,
These are the input B from the bus 5, which is the second addition element, and the carry input C from the carry calculator on the lower bit side. The output is the result of the digit operation. Here, a mask arithmetic unit 13 is arranged for each bit, and input B, which is one of the addition elements, is inputted to a 1-bit arithmetic unit via this mask arithmetic unit 13. These mask calculators 13 are supplied with a 16-bit operation instruction input E from the control logic circuit 8, and when this human power E is supplied, the mask calculators 13 mask the addition element B. . Further, in this example, a carry separation processing unit 14 is arranged between the 200th and 21st bits, and when the control human power F from the control logic circuit 8 is supplied, the 21st bit is transferred from the 200th bit to the 21st bit. Carry to bits is prohibited.

In the 32-bit adder 1 with this configuration, if there is a 16-bit operation instruction from the control logic circuit 8, the upper one
The 6-bit mask operation 313 masks the upper 16 bits of addition element B. As a result, the 32-bit adder l performs an operation on the lower 16 bits, and performs an address calculation within a 6-bit width, that is, 64 bytes. Furthermore, when the control human power F from the control logic circuit is supplied to the carry separation processing unit 14, a carry to the side of bits exceeding the 200th bit is prohibited, so wrap-around is performed at the 1M byte boundary. Addressing becomes possible.

FIG. 4 shows the main components of an address generation device according to another embodiment of the present invention. In this example, a physical address generation device for an instruction briefetch operation performs an address wraparound operation. In the figure, 2
1 is a 32-bit incrementer as a physical address generating means.

This incrementer 21 is supplied with an address generating element from register X via a 32-bit bus 22. The physical address for instruction briefetch generated by this incrementer 21 is sent to the address output via the bus 23. The generated physical address is written back to register X at the same time. 1 determines whether the generated physical address is an address that should cause wraparound.
It is determined by the 6-bit address comparator 24. This comparator 24 compares the generated physical address with the address to which wraparound is to be performed, which is stored in advance in register Y. If the two values match, the wraparound command is sent to the control logic. Output to circuit 25.

In this example, a calculation method is used in which the lower 16 bits of the address to which wraparound should occur and the wraparound destination address are equal, so the address stored in register Y is the wraparound destination address. It also functions as an address that equivalently causes wraparound. Therefore, in this example, when performing a wraparound operation, the value of register Y can be used as is for recalculation as an address generation element.

Here, if there is no relationship as described above between the address where wraparound should occur and the wraparound destination address, as shown in FIG.
It is sufficient to store the wraparound destination address in the register Z and use the contents of register Z as an address generation element for recalculation.

It should be noted that each of the above-mentioned embodiments represents an embodiment of the present invention, and the present invention is not intended to be limited to the configurations of these embodiments. For example, in the above example, a 32-bit adder or a 32-bit incrementer is used as the physical address generating means, but it goes without saying that other means may be used. Further, in the above example, the case where the bit width is 32 bits and 16 bits has been explained, but it goes without saying that this value may be a different number of bits from these. Furthermore, although the bit width of the address generation element is set to two types, 16 bits and 32 bits, it is also possible to use three or more types.

(Effects of the Invention) As explained above, in the present invention, it is determined whether a physical address generated based on an address generation element with a narrow bit width is an address that should be subjected to address wraparound, and If it is the address that should be used, the physical address is generated again so that it becomes the wraparound destination address. Therefore, according to the address generation device of the present invention, it is possible to completely operate a program having a wraparound address space with a narrow bit width. Therefore, it is now possible to generate addresses with a narrow bit width using address generators with a large bit width, which was previously impossible due to bit width incompatibility, and it is now possible to generate addresses with a narrow bit width without discarding old software assets. This has the advantage that it can be used effectively on software.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing the main components of an address generation device according to a first embodiment of the present invention, FIG. 2 is a diagram showing a wrap-around memory area, and FIG. 3 is a diagram showing a wrap-around memory area. FIG. 4 is a partial block diagram showing the configuration of a 32-bit adder of such an address generation device. FIG. 4 is a schematic block diagram showing the main components of an address generation device according to a third embodiment of the present invention. Explanation of symbols - 32-bit adder 2 - Address bus 3 - Memory 4.5 - Bus 6 - Register file 7 - Address comparator 8 - Control logic circuit i Digit calculation of i- Unit I2 -- Carry calculator 13 -- Mask calculator 14 -- Carry separation processing unit 21 -- Incrementer 22.23 -- Bus 24 -- Address comparator 25 -- Control logic circuit.

Claims (2)

[Claims] (1) In a microprocessor address generation device that generates an address space that includes at least a part of a specific area wrapped around so that the maximum address is located directly below the minimum address, a physical address is generated based on at least one address generation element. physical address generation means for generating a physical address, address calculation width specification means for specifying an address calculation width, and when an address calculation width with a smaller number of bits is specified by the address calculation width specification means, the physical address generation means determining means for determining whether the physical address generated by the means is an address to which wraparound should be performed in the specific area; An address generation device for an integrated circuit microprocessor, characterized in that the address generation device for an integrated circuit microprocessor comprises conversion means for converting the generated physical address into a wrap-around destination physical address in the specific area when the address is determined. (2) In the address generation device according to claim 1, the address generation means has an adder with a number of bits corresponding to the number of bits of the maximum width designated by the address calculation width designation means. , each bit constituting this adder is equipped with a 1-bit arithmetic unit and a carry arithmetic unit, and each bit corresponding to at least the minimum width bit number specified by the address calculation width specifying means further An address generation device for an integrated circuit microprocessor, characterized in that the address generation device for an integrated circuit microprocessor is provided with a mask calculator capable of masking input elements input to the 1-bit calculator.