JPS63213888A - Display information processing system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a display information processing device for displaying display data in a video memory in an arbitrary format.

(Prior Art) When displaying characters or graphics on a display device using the Rask scan method, display data stored in a video memory (hereinafter referred to as video RAM) is sequentially read out and displayed on a CRT (F3
A method in which the data is sent to a polar ray tube) and scanned while creating a beam spot of brightness and color corresponding to the display data, as if it were allocated to a display device in video memory and displayed (called the bitmap method). is common.

A block diagram of such a display device is shown in FIG.

7XSJ together with FIG. 5 constitutes the display information processing 5jJ gl according to the prior art. l is central processing 5iHrt(C
PU), 2 is the video RAM 13 is a bus switch, 4 is a bus switching control circuit, 5 is a display address generation circuit, 6 is a timing signal generation circuit, 7 is a digital-to-analog converter, 8
is a display device, 9 is an address bus, 10 is a data bus, !
1 is a CPU stop signal, 12 is a video RAM data bus,
13 is a video RAM address bus, 14 is a bus switching signal, 15 is a display data bus, 16 is a display address bus, 1
7 is a bus switching timing signal, 18 is a display clock signal, 19 is a horizontal blanking period signal, 20 is a vertical blanking period signal,
21 is a display signal.

Further, FIG. 5 is an internal configuration diagram of the display address generation circuit 5 in FIG. 4.

5-1 is a display start address register, 5-2 is a frame buffer width register, 5-3 is an addition 22, 5-4 is a multiplexer, 5-5 is a register, and 5-6 is a display address counter.

The above circuit operates as follows.

The central processing unit 1 (hereinafter referred to as CPU) writes display data to the video RAM 2 using the address 9 and data bus 10. At this time, the bus switching control circuit 4 writes the display data to the video RAM 2 using the address bus 9.
monitors the operation of the CPU, sends a bus switching signal 14 to the bus switching device 3, and switches the video RAM data bus 12 and video RAM address bus 13 of the video RAM 2.
are connected to the data bus 10 and address bus 9, respectively.

The display address generation circuit 5 is connected to a timing signal generation circuit 6.
Display clock signal 18. Horizontally, the display address bus 16 transfers the display data to the video RAM 2. is input to the digital-to-analog converter 7 through the display data bus 15 and sent to the display device 8 as a display signal 21.
Output to and display.

Further, the timing signal generation circuit 6 sends a bus switching timing signal 17 to the bus switching control circuit 4 and
(by switching the display address to the video RA
M2, and the display data is supplied to the digital/analog converter 7 (at this timing,
If the CPU attempts to read the video RAM 2, the bus switching fliIIr8 circuit 4
A CPU stop signal 11 is sent to I, the CPU is stopped, and reading and writing by the CPU is executed after reading of display data is completed.

Further, the display address generation circuit 5 shown in FIG. 5 operates as follows.

When the display timing is during the vertical retrace period, the contents of the display start address register 5-1 are transferred to the multiplexer 5-4.
is supplied to the register 5-5 by the horizontal retrace period signal 19, and is written to the register 5-5 by the horizontal retrace period signal 19. The contents of the register 5-5 at this time are the values DS A (D +5pl
ay Start Address) is set.

Further, the output of this register 5-5 is connected to a display address counter 5-6, and the value of the register 5-5 is loaded in accordance with the horizontal fi period signal 19. Therefore, like the register 5-5, the value is DSA during the vertical retrace period.

Next, in the display period, the display clock 18 is input to the display address color/receiver 5-6, and the display clock 18 is incremented as DSA, DSA+1, DSA+2, . . . . The output of the display address counter 5-6 is input to the video RAM 2 via the display address bus 10, and display data at this display address is read out and sent to the display device. In this way, the display continues for the first horizontal display period, and then enters the horizontal retrace period. In this case, multiplexer 5-4 is vertical *a! ! ;! Already switched by the period signal 20, the adder 5-
3 is input to the register 5-5, the horizontal retrace period signal 19 changes the contents of the register s-s DsA
, the contents of the frame buffer width register 5-2, FRW
th), the added value "DSA+FI3W" is loaded into the register 5-5 display address counter 5-6.

In this way, when the next horizontal display period begins, the display address counter 5-6 will display DSA+FnW, DSA+FnW+1,
. . , and the contents of the video RAM 2 are displayed. This barking situation is shown in Figure 6. That is, the display address increases in sequence in the horizontal direction of the display, and increases by the width (FnW) of the frame buffer in the vertical direction. In this way, the contents of the video RAM 2 can be displayed on the display device 8.

Furthermore, the contents of the display start address register 5-1 are CP
Video RAM can be rewritten using the UI.
By moving (scrolling) the displayed content in the water T or vertical direction, or by setting the frame buffer width register 5-2 to the desired value,
By preparing a screen corresponding to a number of pages on the display screen and rewriting the contents of the display start address register 5-1, the display contents can be switched in an instant.

[Problem to be Solved by the Invention 1] In the display device described above, when the contents of the display screen are scrolled in one direction or in the vertical direction, the following problem occurs.

Figure 7 (a) shows a display in which the horizontal width of the frame buffer is set larger than the area displayed by the display device, the display start address register 5-1 is set appropriately, and the display area is on the left side in the video RAM 2. This shows the state in which this is being carried out.

Next, display data to be displayed on the display device 8 after scrolling is written in advance in a portion of the area A that is not displayed on the display device 8.

Next, as shown in FIG. 7(b), if the contents of the display address υ) 1 start register 5-1 are set and the value of DSA is increased,
On the display device 8, it appears as if the screen has moved to the left.

When the DSA is set as shown in FIG. 7(C) using similar means, the screen appears to move further to the left, but it is not possible to continue increasing the DSA beyond this state.

If set, as shown in FIG. 7(d), since the display address during the horizontal display period increases continuously,
After the address, the contents of the Z address are displayed instead of the contents of the Y address. That is, if settings are made such that the display area protrudes from the frame buff 71 of the video RAM 2, the display of the protruding portion will be the content of the area in which the address has been increased by FIlW. For this,(
I) Display data in the scroll destination non-display area 11'<
.

1) Increase and display the display address (DSA).

By repeating this, if you continue horizontal scrolling, the display f, 1
7 M moves in the vertical direction of the frame buff 1, and a problem occurs in which the display area eventually moves out of the video RAM 2.

Therefore, after scrolling from (a) to (b) to (c) in FIG. 7, the contents of the display area in (c) are transferred to the display area in (a), and the same operation is repeated again.

This means that the amount of work required for the scrolling operations in Figure 7 (a) and (b) is compared to the work of writing display data to the frame buffer area that appears after scrolling and increasing the DSA value. In order to scroll from C) to (a), display data for approximately one display screen must be transferred, which takes a lot of time, and only at this time the screen scrolling operation becomes slow. Therefore, the scrolling operation is not smooth (it is difficult to see, so the steps from (a) to (b)
, it is necessary to set a waiting time when scrolling from (b) to (C), and make it the same time as scrolling from (C) to (a). In the end, the DSA value is fixed and the entire screen is displayed. There is no difference in performance compared to when data is transferred and scrolled. The same thing also happens when scrolling in the vertical direction.

A further problem is that when the contents of the video RAM being displayed are transferred, a part of the screen appears scrolled during the vertical display period, causing the picture to undulate or flicker, making the display screen smoother. The impression of movement will fade, so in order to scroll without flickering, create display data for two screens in the video RAM as shown in Figure 8, set area 1 as the display area, and set area 2's display data as the display area. After the data is transferred by the CPU and the display data is moved, the display area is switched to the area 2 side as shown in FIG. 8(b), and the display data on the area 1 side is then transferred. By repeating this process, it is possible to scroll without flickering, but the video RA of the 2M screen area is
M is required.

That is, when performing scrolling on a conventional display device, there are disadvantages in that an extra video RAM area is required and the scrolling performance is low.

This is because display addresses are generated continuously, so it is not possible to wrap around the display area...like a conveyor belt, and rotate the display area at the same time.

Furthermore, even if some conventional display devices are capable of wrapping around in the horizontal and vertical directions, the horizontal and vertical sizes of the frame buffer are actually fixed, so the display shape is optimal. Unable to set minimum framebuffer in .

In other words, it has the disadvantage of lacking flexibility in use.

An object of the present invention is to provide an inexpensive display device with high flexibility in display settings that allows high-speed scrolling even when the amount of video RAM used is small.

[Means for solving problems]

The control method of the present invention provides a display information processing device that includes at least a central processing unit that creates display data and a circuit that reads display data from a memory that reads the created display data. A certain area is set as a first area, a certain area inside this first area is designated as a second area, and this is read out and output as display data to a display device, and upon reading out, By setting and reading a predetermined address for the second area protruding from the first area inside the memory, the minimum display memory can be rewritten to match the display shape of the display unit. Enables you to scroll around the wrap.

[Effect]

In the present invention, the start address of the frame buffer 7 (F S
A: Frage Buyer Start
address) and next to the frame buffer [(F
BW) and the vertical width of frame buffer 1 (FBL:
CP
U uses a register whose setting value can be changed to store a two-dimensional area in the video RAM in addition to the display area as frame buffer 1.
In this frame buffer, specify the display start address (DSA) and the start address of frame buffer 1 (
X offset (OF X : OF r
set-X) and X offset (OF Y: OF
The area to be displayed on the display device is specified by the registers of rset-Y) whose setting values can be varied by CI'U, and the display area outside the frame buffer area is set horizontally as "FI3W-OFX"! r! f1
The direction is detected from the setting value of "FDL-OFY", and the start address of the display area that protrudes horizontally from the frame buffer 1 area is set as "DSA-OFX", and the start address of the display area that also protrudes vertically from the frame buffer 1 area is set as "DSA-OFX". FSA+OF
It has means for setting the start address of the display area that protrudes simultaneously in the horizontal and vertical directions as "FSA".

The above configuration enables wrap-around scrolling, which allows scrolling to be performed by simply rewriting the minimum amount of display memory, and allows the frame buffer surface to be set according to the displayed tooth, resulting in low cost and high performance. A highly flexible display information processing device can be realized.

〔Example〕

1 and 2 are examples of the present invention.

1 and 2 are detailed diagrams of the display address generation circuit 5, and 2-1 is a horizontal width register (FBW) of the frame buffer 1.
), 2-2 is the display start address register (DSA>, 2
-3 is the X offset register (OFX), 2-4 is the start address register (FSA) of frame buffer 7, 2-
5 is a subtractor, 2-6.2-7.2-8.2-9.2-1
0 is adder, 2-11.2-12.2-13.2-14
is a multiplexer, 2-15 is register 1, 2-16 is register 2, 2-17 is register 3, and 2-18 is register 4.

Figure 2 3-1 shows the frame buffer width register (FD
W), 3-2 is the X offset register (OFX), 3-
3 is the vertical width register (FBL) of the frame buffer, 3-
4 is the X offset register (01'Y), 3-6.3-
7 is a subtracter, 3-8 is a horizontal counter, 3-0 is a vertical counter, 3-10 is a multiplexer, and 3-11 is a display address color.

These perform the following operations.

First, during the vertical line period, multiplexer 2-
11.2-12 are display start addresses (DS
A), (display address) - (X Off Cebu)) (DSA-
OFX) is selected, and register 1.
2-15 and register 2.2-16 are loaded with their respective addresses.

Also, the frame buffer width register (FDW) in Figure 2
>3-1 to X offset register (OFX)3-2
is subtracted by the subtractor 3-6 and loaded into the horizontal color register 3-8 by the horizontal retrace signal 19. This horizontal counter 3-8 is decremented every time the display clock 18 is input, and when the content is other than "On", the signal A is set to θ".
is configured to output "1n" as the signal A when the content is "0".

Also, frame buffer vertical width register (FBL) 3-
3, the contents of the X offset register (OF Y ) 3-4 are subtracted by the subtractor 3-7 and loaded into the vertical counter 3-9 by the vertical retrace signal 20. Like the horizontal counter 3-8, this vertical counter 3-9 is decremented by the horizontal blanking period signal 19, and when the content is other than "ON", the signal B is "0", and when the content is "0", the signal B is "0". It is configured to output "1" to signal B.

Next, when the display period begins, the signals A and Il input to the multiplexer 3-10 are sent to the horizontal counter 3-8. Since none of the contents of the vertical counters 3-0 are "01", it is assumed that they are each "0". In this case, multiplexer 3-10 outputs signal 1, i.e. register 1,
Display start address (DSA) set in 2-5
) is loaded into the display address counter 3-11, and according to the display clock 18, DSA, DSA+1°DS
A+2. ...and outputs the display address.

If the display area is set so that it does not protrude horizontally from the area of the width (F[3W) of the frame buffer 7 and the vertical width (FBL) of the frame buffer 7, as shown in Figure 3 (a>), During the horizontal display period, the content of the horizontal counter 3-8 does not become "0" and the signal A remains "0", and the multiplexer 3-10 continues to select the signal rlJ. Similarly to the conventional display address generation circuit 5 shown in FIG. 4, the circuit continues to output continuous display addresses during one horizontal display period.

If the setting of the display area extends horizontally as shown in Figure 3(b), the content of the horizontal counter 3-8 becomes 0'' during the horizontal display period, and the signal A changes to 1. Then, the multiplexer 3-10 selects the signal "2" and displays the contents of the register 2.2-16 (DSA) on the display address counter 3-11.
-OFX). It can be seen that this address is different from the display address of the conventional system, and is a display address located on the same horizontal coordinate line as the DSA on the mapping of the video RAM, as shown in FIG. 3(b).

In other words, the display gA@ has horizontally wrapped around within the frame buff area. In this way, the display address counter 3-11 increments from the DSA-OFX address and then enters the horizontal retrace period. Then, multiplexers 2-11 and 2-12 select the side of the value obtained by adding the width (FI3W) of 7 frame buffer 1 to the contents of registers 1.2-15 and 2.2-16, so Registers 1.2-15 contain DSA
+ FDW, register 2.2-1 (3 has DSA-O
The values of FX+FIIW are loaded respectively. In this way, display is performed during the horizontal display period, and the contents of registers 1.2-15 and 2-16 are changed in the vertical direction by adding FIIW every time the horizontal retrace period begins. Also, display addresses for the DSA system and DSA-OFX system are generated, and display is performed until the vertical retrace period, and the state returns to the original V state.

Next, a case where the display area does not protrude from the frame buffer area in the vertical direction as shown in FIG. 3(e) will be described. At this time, the horizontal counter 3-8 is kQ during the horizontal display period.
+l does not occur, and the signal A remains at "0". Since the vertical counter 3-9 is not “0”, the signal B is
IO”. Therefore, multiplexer 3-1
0 selects the DSA system address in registers 1.2-15 and generates a display address. Further, as the horizontal display period is repeated, the contents of the vertical color/reference signal 3-9 are decremented, and when it becomes '0#, the signal B becomes "1". Then, multiplexer 3-10 selects signal "3",
Display contents of register 3.2-17 Address counter 3
-11. Register 3.2-17 and register 4.2-18 are respectively loaded with FSA+OFX and FSA a through multiplexer 2-13.2-14, and signal B becomes 1'', register 3.2-18.
17 and the outputs of registers 4.2-18, respectively)
It is switched to the side of the value obtained by adding W.

Therefore, in the next horizontal retrace period, each FSA+OF
X+F[lW, FSA+FBW (1) value is a-coded. Also, the FSA+ loaded in register 3.2-17
The value of OFX is a display address on the same vertical coordinate on the frame buffing area, that is, vertical wrap-around. In this way, the display address for the next horizontal display period is generated, and Ft3W is continued to be added every horizontal retrace period, and the program enters the vertical retrace period and returns to the original inoculation.

(Similarly, in the case of horizontal and vertical wraparound in FIG. 3(d), in the first horizontal display period, register 1
．． 2-15 DSA addresses are used. In the middle of the horizontal display period, the horizontal counter 3-8 becomes "11O", the signal A becomes "1", and the multiplexer 3-10 loads the DSA-OFX address of the register 2.2-18 into the display counter 3-11. to generate the display address.

Next, registers 1, 2-15. Register 2.2-16
The content of the vertical counter 3-9 is decremented and becomes "0", and the signal B becomes "1". At this time, the horizontal counter 3-8 loads the F BW-OF X again, so the signal A becomes #0''. After the next horizontal display period starts, since the value of FSA+OFX is stored in the display address counter 3-11, the display addresses are displayed in order from this display address. When the content of the horizontal counter becomes "θ", the signal A becomes "1", so the multiplexer 3-10 selects the register 4.2-18 of the signal "4", and displays the FSA in the display address column 3. -11 and display it.

In the manner described above, display can be performed in which the display area wraps around horizontally and vertically.

In the above embodiment, the display disclosure address (DSA) is the CPU
Although it was explained as a register set by DSA=FSA
The circuit configuration may be such that the DSA is automatically calculated from the relational expression +OFX+FBWXOFY.

Also, addition of FI13W to DSA, FSA, OFX, FBW-OFX, FIIL-OFL, C3A-0F
Operations such as X, FSA+OFX, etc. may be calculated by a microprogram or software and provided directly to each register or counter.

[Action of the invention]

In order to generate display addresses with the above configuration, the conventional circuit performs horizontal crawling in Figures 8(a) and 8(a).
Even if you do not scroll while switching the display memory for two screens as shown in b), the portion that protrudes from the frame buffer area due to the secret in FIG. 7(b) is i! ! Since this is a wrap-around area, (I) displays display data in the non-display area at the scroll destination, (n) display disclosure address (DSA) and X offset (O
PX), but if OFX is FBW
If it becomes larger, horizontal wraparound can be performed by simply repeating the procedure of setting the first address of the horizontal display address as DSA and setting OFX as "0 call." It is exactly the same when performing the DSA and OFY.
It is sufficient to control within the region of L. If you do this,
Scrolling can be achieved by rewriting the minimum memory area. Therefore, even with a display memory, it is possible to realize a display information processing device that is fast and has high flexibility in display states.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a display address generation circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a main part of a display address generation circuit according to an embodiment, and FIG. 3 is a circuit diagram showing a display address generation circuit according to an embodiment of the present invention.・A diagram showing the around state, Figure 4 is a circuit diagram showing the entire conventional display address generation circuit, Figure 5 is a circuit diagram of the main part of the conventional display address generation circuit, and Figure 6 is the display timing and display of the conventional method. FIG. 7 is an explanatory diagram of addresses, FIG. 7 is an explanatory diagram of display timing in a conventional method, and FIG. 8 is a diagram showing an example of a horizontal scrolling method according to another conventional method. 1 Central processing unit (CPU) 2 Video RAM
3 Bus switching device 4 Bus switching control circuit 5 Display address generation circuit 6 Timing signal generation circuit 7 Digital-to-analog converter 8 Display device 9
Address bus 10 Dark bus 11 CPU stop signal 12 Video RAM M data bus 13 Video RAM address bus 14 Bus switching signal 15 Display data bus 16 Display address bus I7 Bus switching timing 18 Display clock signal 10 Horizontal retrace period signal 20
Tare 1 [! Blank line period signal 21 Display signal 2-1 Frame buffer width register 2-2 Display start address register 2-3 X offset register 2-4 Frame buffer 1 start address register 2-5
Subtractor 2-6.2-7.2-8.2-9.2-10 Adder 2-11.2-12.2-13.2-14 Multiplexer 2-15 Register 12-16 Register 2
2-17 Register 32-18 Register 4 3-1 Frame buffer width register 3-2 X offset register 3-37 Frame buffer vertical width register 3-4 Y offset register 3 6.3-7 Subtractor 3-8 Horizontal Counter 3-9 Vertical counter 3-1
0 multiplexer

Claims (1)

[Scope of Claim] A display information processing device comprising at least a central processing unit that creates display data, a memory that stores the created display data, and a circuit that reads display data from this memory, comprising: A specified area is set as the first area, a certain area inside the first area is specified as the second area, and this is read out to output as display data to the display, and the readout is performed. On the occasion of
By setting and reading a predetermined address to a second area protruding from the first area on the inside of the memory, the minimum display memory can be simply rewritten according to the display state of the display. A display information processing method characterized by enabling wrap-around scrolling.