JPH03141691A - Manufacture of lead terminal of ceramic circuit board - Google Patents
Manufacture of lead terminal of ceramic circuit boardInfo
- Publication number
- JPH03141691A JPH03141691A JP28136789A JP28136789A JPH03141691A JP H03141691 A JPH03141691 A JP H03141691A JP 28136789 A JP28136789 A JP 28136789A JP 28136789 A JP28136789 A JP 28136789A JP H03141691 A JPH03141691 A JP H03141691A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- pattern
- circuit board
- thick film
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000004020 conductor Substances 0.000 claims abstract description 46
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052802 copper Inorganic materials 0.000 claims abstract description 22
- 239000010949 copper Substances 0.000 claims abstract description 22
- 238000005520 cutting process Methods 0.000 claims abstract description 14
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 238000009792 diffusion process Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 11
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 8
- 238000007639 printing Methods 0.000 claims description 6
- 229910052763 palladium Inorganic materials 0.000 claims description 4
- 238000010304 firing Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 230000004907 flux Effects 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- YCKOAAUKSGOOJH-UHFFFAOYSA-N copper silver Chemical compound [Cu].[Ag].[Ag] YCKOAAUKSGOOJH-UHFFFAOYSA-N 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
セラミック回路基板のリード端子製造方法に関し、
リード端子を回路パターンと一体形成し接続箇所を減ら
すことを目的とし、
セラミック基板の後工程で切断除去される端部セラミッ
ク基板の表面上に銀−パラジウム導体ペーストをパター
ン印刷する工程と、該銀−パラジウム導体ペーストΦ上
及び前記切断除去後に残るセラミック基板の表面上に厚
膜回路パターンとなる銅導体ペーストをパターン印刷す
る工程と、前記銅導体ペーストから銅導体及び前記銀−
パラジウムと銅とを金属拡散結合し剥離可能な銅−銀−
パラジュウム金属の厚膜導体を形成する加熱焼成工程と
、該形成した厚膜導体下の前記端部セラミツク基板を切
断除去する工程を含み、前記残るセラミック基板上に前
記銅導体からなる厚膜回路パターンと外方に突出する前
記厚膜導体からなるリード端子とを一体して形成するよ
うに構成する。[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing lead terminals of a ceramic circuit board, the purpose is to reduce the number of connection points by forming the lead terminals integrally with the circuit pattern, and to reduce the number of connection points by forming the lead terminals integrally with the circuit pattern. A step of pattern printing a silver-palladium conductor paste on the surface of a ceramic substrate, and a pattern printing of a copper conductor paste to become a thick film circuit pattern on the silver-palladium conductor paste Φ and on the surface of the ceramic substrate remaining after the cutting and removal. and a step of forming a copper conductor and the silver conductor from the copper conductor paste.
Peelable copper-silver by metal diffusion bonding of palladium and copper
A thick film circuit pattern made of the copper conductor is formed on the remaining ceramic substrate, including a heating and firing step of forming a thick film conductor of palladium metal, and a step of cutting and removing the end portion of the ceramic substrate under the formed thick film conductor. and an outwardly protruding lead terminal made of the thick film conductor are integrally formed.
本発明はセラミック回路基板のリード端子製造方法に関
する。The present invention relates to a method for manufacturing lead terminals for ceramic circuit boards.
電子回路モジュールを構成するマザー回路基板とサブ回
路基板とを電気接続するのに、それぞれに設けた外部接
続用電極（端子、ランド）同士を別の単体導線で半田付
は接続する場合がある。その場合、半田付は箇所は２箇
所となり半田付は作業の能率上の問題、半田フラックス
の洗浄の問題があり、電気的接続の信頼性を確保する観
点から接続箇所を減らすことが要望されている。To electrically connect a mother circuit board and a sub-circuit board constituting an electronic circuit module, external connection electrodes (terminals, lands) provided on each may be connected to each other by soldering using separate conductive wires. In that case, there are two points to be soldered, and there are problems with soldering work efficiency and cleaning of the solder flux.Therefore, it is desired to reduce the number of points to be connected in order to ensure the reliability of the electrical connection. There is.
従来は第３図！ａ）、 （ｂ）、 （Ｃ１，（ｄ）の側
断面図のように、高発熱する電子部品１４、例えば半導
体素子などをエポキシ樹脂積層基板などからなるマザー
回路基板１３に搭載実装する場合、半導体素子１４の熱
膨張係数に合わせ放熱を良くするため、回路パターン（
図示路）を形成したセラミック基板１１ａからなるサブ
回路基板１１に一旦、グイボンディング（（ａ）図参照
）した後、サブ回路基板１１のランド１１ａ−１とワイ
ヤボンディング（（ｂ）図参照）し、さらに耐湿及び汚
染防止のため樹脂材をボッティング（（Ｃ）図参照）し
、つぎにサブ回路基板１１を熱硬化性接着剤１５でマザ
ー回路基板１３に固着した後、サブ回路基板１１の外部
接続用電極１１ａ−２とマザー回路基板１３の外部接続
用ランド１３ａとを単体の導線１６で半田付は接″Ｉｆ
ｔ（ｆｄ１図参照）している。Previously, it was Figure 3! As shown in the side cross-sectional views of a), (b), (C1 and (d)), when electronic components 14 that generate high heat, such as semiconductor elements, are mounted on a mother circuit board 13 made of an epoxy resin laminated board or the like, In order to improve heat radiation according to the thermal expansion coefficient of the semiconductor element 14, the circuit pattern (
After first performing wire bonding (see figure (a)) on the sub-circuit board 11 made of the ceramic substrate 11a on which the circuit (as shown in the figure) is formed, wire bonding is performed with the land 11a-1 of the sub-circuit board 11 (see figure (b)). Furthermore, after botting a resin material for moisture resistance and pollution prevention (see figure (C)), and then fixing the sub-circuit board 11 to the mother circuit board 13 with a thermosetting adhesive 15, the sub-circuit board 11 is The external connection electrode 11a-2 and the external connection land 13a of the mother circuit board 13 are soldered using a single conductive wire 16.
t (see figure fd1).
しかしながら、このような単体導線を用いて接続する上
記構成、方法によれば、各導線に対し接続点は２箇所と
なり、また半導体素子への悪影響がないようにフラフク
スの洗浄をする必要もあって作業能率も悪いといった問
題があった。However, according to the above-mentioned configuration and method of making connections using such single conductor wires, there are two connection points for each conductor wire, and it is also necessary to clean the flux to prevent it from having an adverse effect on the semiconductor elements. There was also the problem of poor work efficiency.
上記問題点に鑑み、本発明はリード端子を回路パターン
と一体形成し接続箇所を減らすことのできるセラミック
回路基板のリード端子製造方法を提供することを目的と
する。In view of the above-mentioned problems, an object of the present invention is to provide a method for manufacturing lead terminals of a ceramic circuit board in which lead terminals are integrally formed with a circuit pattern and the number of connection points can be reduced.
上記目的を達成するために、本発明のセラミック回路基
板のリード端子製造方法においては、セラミック基板の
後工程で切断除去される端部セラミック基板の表面上に
銀−パラジウム導体ペーストをパターン印刷する工程と
、該銀−パラジウム導体ペーストの上及び前記切断除去
後に残るセラミック基板の表面上に厚膜回路パターンと
なる銅導体ペーストをパターン印刷する工程と、前記銅
導体ペーストから銅導体及び前記恨−パラジウムと銅と
を金属拡散結合し剥離可能な銅−銀−パラジュウム金属
の厚膜導体を形成する加熱焼成工程と、該形成した厚膜
導体下の前記端部セラミック基板を切断除去する工程を
含み、前記残るセラミック基板上に前記銅導体からなる
厚膜回路パターンと外方に突出する前記厚膜導体からな
るリード端子とを一体して形成するように構成する。In order to achieve the above object, the method for manufacturing lead terminals of a ceramic circuit board of the present invention includes a step of pattern-printing a silver-palladium conductive paste on the surface of the ceramic substrate at the end portions to be cut and removed in a subsequent process of the ceramic substrate. a step of pattern printing a copper conductor paste to form a thick film circuit pattern on the silver-palladium conductor paste and on the surface of the ceramic substrate remaining after the cutting and removal; and copper by metal diffusion bonding to form a peelable copper-silver-palladium metal thick film conductor, and a step of cutting and removing the end ceramic substrate under the formed thick film conductor, The thick film circuit pattern made of the copper conductor and the lead terminal made of the thick film conductor protruding outward are integrally formed on the remaining ceramic substrate.
端部が剥離可能な回路パターンをセラミック基板上に形
成した後、回路パターン端部下のセラミック基板を一部
切断除去することにより、回路パターンの端部をセラミ
ック基板から外方に突出させ外部回路基板に直接、電気
接続することのできるリード端子を形成することができ
、回路パターンと一体したリード端子を備えるセラミッ
ク回路基板を製造することができる。After a circuit pattern with peelable ends is formed on a ceramic substrate, a portion of the ceramic substrate below the ends of the circuit pattern is cut and removed, thereby allowing the ends of the circuit pattern to protrude outward from the ceramic substrate, thereby creating an external circuit board. It is possible to form lead terminals that can be electrically connected directly to the ceramic circuit board, and to manufacture a ceramic circuit board that includes lead terminals that are integrated with a circuit pattern.
以下図面に示した実施例に基づいて本発明の要旨を詳細
に説明する。The gist of the present invention will be explained in detail below based on embodiments shown in the drawings.
第１図（ａ）、 （ｂ）、 （ｃ）、 ｆｄ）は本発明
によるセラミック回路基板のリード端子製造方法を工程
順に側断面図で示すもので、
（８１図はセラミック基板１ａの後工程で切断除去され
る端部セラミック基板１ａ−２の表面上に次工程の銅導
体ペースト２ｂと共に焼成してリード端子を形成する銀
−パラジウム導体ペースト２ａをパターン印刷した状態
を、
（ｂ）図は銀−パラジウム導体ペースト２ａの上及び切
断除去後に残るセラミック基板１ａ−１の表面上に焼成
して回路パターンを形成する銅導体ペース１−２ｂをパ
ターン印刷した状態を、
（Ｃ）図は７００〜１０００℃の温度で加熱焼成し恨〜
パラジウム導体ペースト２ａと銅導体ペースト２ｂを金
属拡散結合し剥離可能（図示するように端部セラミック
回路基板１ａ−２の表面から浮き上がってくる）なり一
ド端子となる銅−銀一パラジュウムの厚膜導体２ａｂと
厚膜回路パターンとなる銅導体２を一体形成し厚膜導体
２ａｂ下の端部セラミック基板１ａ２を切断するための
ブレイク溝１ｂを入れた（（ａ）図のペースト塗布工程
前に予め、入れておいてもよい）状態を、
（ｄｌ図はブレイク溝１ｂから両端部セラミック基板１
ａ−２を切断除去して残るセラミック基板１８−１上に
厚膜回路パターン（銅導体）２と外方に突出するリード
端子（ｆｆｌｌ！導体）２ａｌ）を一体形成した状態を
示す。Figures 1 (a), (b), (c), fd) are side sectional views showing the method for manufacturing lead terminals for ceramic circuit boards according to the present invention in the order of steps; The figure (b) shows a state in which a pattern of silver-palladium conductor paste 2a is printed on the surface of the end ceramic substrate 1a-2 to be cut and removed in the next step, which is fired together with the copper conductor paste 2b to form lead terminals. Figure (C) shows a state in which a pattern of copper conductor paste 1-2b, which is to be fired to form a circuit pattern, is printed on silver-palladium conductor paste 2a and on the surface of ceramic substrate 1a-1 remaining after cutting and removal. Heat and bake at a temperature of 1000℃~
The palladium conductor paste 2a and the copper conductor paste 2b are bonded by metal diffusion and are peelable (as shown in the figure, they rise from the surface of the end ceramic circuit board 1a-2) to form a copper-silver-palladium thick film that becomes a single lead terminal. The conductor 2ab and the copper conductor 2 that will become the thick film circuit pattern are integrally formed, and a break groove 1b for cutting the end ceramic substrate 1a2 under the thick film conductor 2ab is formed (previously before the paste application process in Figure (a)). , may be left in) state, (dl diagram shows both ends of ceramic substrate 1 from break groove 1b
A thick film circuit pattern (copper conductor) 2 and a lead terminal (ffll! conductor) 2al) projecting outward are integrally formed on the ceramic substrate 18-1 remaining after cutting and removing a-2.
以上の工程により厚膜回路パターン２と一体形成した厚
さ１〜１００ μｍ範囲のリード端子２ａ１）を備える
セラミック回路基板１を製造することができる。Through the above steps, it is possible to manufacture the ceramic circuit board 1 including the lead terminals 2a1) integrally formed with the thick film circuit pattern 2 and having a thickness in the range of 1 to 100 μm.
つぎに、第２図（ａｌ、 （ｂ）、 （Ｃ１，（ｄ）は
第１図の（ｄｌ図に続いてセラミック回路基板１をマザ
ー回路基板３に搭載実装する工程順を側断面図で示すも
ので、ｉａ１図はセラミック回路基板１のリード端子２
ａｂをマザー回路基板３のランド３ａに接続できるよう
にフォーミングした状態を、
（ｂ１図はセラミック回路基板１上に高発熱する電子部
品４、例えば半導体素子をダイボンディングした状態を
、
（Ｃ）図はセラミック回路基板１の厚膜回路パターン２
に半導体素子４をワイヤボンディングした後、耐湿及び
汚染防止のため樹脂材をボッティングした状態を、
（ｄｌ図はマザー回路基Ｆｉａ上にリード端子２ａｂを
ランド３ａに位置合わせしてセラミック回路基板ｌを熱
硬化性接着剤５で固着し、リード端子２ａｂをランド３
ａに共晶合金などにより熱圧着（あるいは半田付けでも
よい）した状態を示す。Next, Figures 2 (al, (b), (C1, d) are side sectional views showing the process order of mounting and mounting the ceramic circuit board 1 on the mother circuit board 3, following Figure 1 (dl). The ia1 diagram shows the lead terminals 2 of the ceramic circuit board 1.
Figure B1 shows the state in which ab is formed so that it can be connected to the land 3a of the mother circuit board 3. (Figure B1 shows the state in which electronic components 4 that generate high heat, such as semiconductor elements, are die-bonded on the ceramic circuit board 1. Figure (C) is the thick film circuit pattern 2 of the ceramic circuit board 1
After wire-bonding the semiconductor element 4, the resin material is bonded to prevent moisture and contamination. are fixed with thermosetting adhesive 5, and lead terminal 2ab is attached to land 3.
Figure a shows a state in which the parts are bonded by thermocompression (or may be soldered) using a eutectic alloy or the like.
このように端部が剥離可能な回路パターンをセラミック
基板上に形成した後、回路パターン端部下のセラミック
基板を一部切断除去することにより、回路パターンの端
部をセラミック基板から外方に突出させ外部回路基板に
直接、電気接続することのできるリード端子と回路パタ
ーンとを備えるセラミック回路基板を製造することがで
き、リード端子の接続箇所を１箇所とすることができる
。After forming a circuit pattern with removable ends on a ceramic substrate in this way, the ends of the circuit pattern are made to protrude outward from the ceramic substrate by cutting and removing a portion of the ceramic substrate below the ends of the circuit pattern. A ceramic circuit board can be manufactured that includes a lead terminal and a circuit pattern that can be electrically connected directly to an external circuit board, and the lead terminal can be connected to only one location.
このセラミック回路基板を第２図で説明したようにサブ
回路基板とし、別途製作したマザー回路基板に搭載実装
する場合は、例えばＴ Ａ Ｂ （Ｔａｐｅ八ｕｔへｍ
ａｔｅｄ Ｂｏｎｄｊｎｇ）技術によりリード端子の先
端を熱圧着（あるいは半田付け）接合するだけで済むた
め、作業能率が向上し、半導体素子へのフラックスの悪
影響も避けられ、電気的接続の信頼性を向上することが
できる。When this ceramic circuit board is used as a sub-circuit board as explained in Fig. 2 and is mounted on a separately manufactured mother circuit board, for example, T A B
ated bonding technology, it is only necessary to join the tips of the lead terminals by thermocompression (or soldering), which improves work efficiency, avoids the negative effects of flux on semiconductor elements, and improves the reliability of electrical connections. be able to.
以上、詳述したように本発明によれば、セラミック回路
基板のリード端子を回路パターンと一体形成することが
でき、作業能率を向上して安価で信顛度の高い電子回路
モジュール等を提供することができるといった産業上極
めて有用な効果を発揮する。As detailed above, according to the present invention, the lead terminals of the ceramic circuit board can be integrally formed with the circuit pattern, improving work efficiency and providing an inexpensive and highly reliable electronic circuit module. It exhibits an extremely useful effect industrially.
第１図（ａｌ、 （ｂ）、 （Ｃ１，（ｄｌは本発明に
よる一実施例を工程順に示す側断面図、
第２図（ａｌ、 （ｂ）、 （Ｃ１，（ｄ）は第１図を
マザー回路基板に搭載実装する工程順を示す側断面図、
第３図ｆａｎ、 （ｂ）、 （ｃＬ （ｃｇは従来技術
による側断面図である。
図において、
■はセラミック回路基板、
１ａはセラミック基板、
１ａ−１は残部セラミック基板、
１ａ−２は端部セラミック基板、
２は厚膜回路パターン（銅導体）、
２ａは銀−バラジュウム導体ペースト、２ｂは銅導体ペ
ースト、
２ａｂはリード端子（厚膜導体）を示す。
凶Fig. 1 (al, (b), (C1, (dl) is a side sectional view showing an embodiment of the present invention in the order of steps, Fig. 2 (al, (b), (C1, (d) is Fig. 1) A side sectional view showing the process order of mounting and mounting on the mother circuit board,
Fig. 3 fan, (b), (cL (cg is a side sectional view of the conventional technology. In the figure, ■ is a ceramic circuit board, 1a is a ceramic substrate, 1a-1 is the remaining ceramic board, 1a-2 is an end 2 is a thick film circuit pattern (copper conductor), 2a is a silver-baladium conductor paste, 2b is a copper conductor paste, and 2ab is a lead terminal (thick film conductor).
Claims (1)
セラミック基板（１ａ−２）の表面上に銀−パラジウム
導体ペースト（２ａ）をパターン印刷する工程と、該銀
−パラジウム導体ペースト（２ａ）の上及び前記切断除
去後に残るセラミック基板（１ａ−１）の表面上に厚膜
回路パターン（２）となる銅導体ペースト（２ｂ）をパ
ターン印刷する工程と、 前記銅導体ペースト（２ｂ）から銅導体（２）及び前記
銀−パラジウムと銅とを金属拡散結合し剥離可能な銅−
銀−パラジュウム金属の厚膜導体（２ａｂ）を形成する
加熱焼成工程と、 該形成した厚膜導体（２ａｂ）下の前記端部セラミック
基板（１ａ−２）を切断除去する工程を含み、前記残る
セラミック基板（１ａ−１）上に前記銅導体（２）から
なる厚膜回路パターンと外方に突出する前記厚膜導体（
２ａｂ）からなるリード端子とを一体して形成すること
を特徴とするセラミック回路基板のリード端子製造方法
。[Claims] A step of pattern-printing a silver-palladium conductive paste (2a) on the surface of an end ceramic substrate (1a-2) which is cut and removed in a subsequent process of the ceramic substrate (1a); pattern-printing a copper conductor paste (2b) that will become a thick film circuit pattern (2) on the palladium conductor paste (2a) and on the surface of the ceramic substrate (1a-1) remaining after the cutting and removal; The copper conductor (2) and the silver-palladium and copper are metal diffusion bonded from the paste (2b) and can be peeled off.
a heating and firing step of forming a thick film conductor (2ab) of silver-palladium metal; and a step of cutting and removing the end ceramic substrate (1a-2) under the formed thick film conductor (2ab); A thick film circuit pattern consisting of the copper conductor (2) and the thick film conductor (2) protruding outward are arranged on the ceramic substrate (1a-1).
A method for manufacturing a lead terminal for a ceramic circuit board, characterized in that the lead terminal is formed integrally with a lead terminal consisting of 2ab).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28136789A JPH03141691A (en) | 1989-10-26 | 1989-10-26 | Manufacture of lead terminal of ceramic circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28136789A JPH03141691A (en) | 1989-10-26 | 1989-10-26 | Manufacture of lead terminal of ceramic circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03141691A true JPH03141691A (en) | 1991-06-17 |
Family
ID=17638134
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28136789A Pending JPH03141691A (en) | 1989-10-26 | 1989-10-26 | Manufacture of lead terminal of ceramic circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03141691A (en) |
-
1989
- 1989-10-26 JP JP28136789A patent/JPH03141691A/en active Pending
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