JPH03136358A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03136358A JPH03136358A JP27684889A JP27684889A JPH03136358A JP H03136358 A JPH03136358 A JP H03136358A JP 27684889 A JP27684889 A JP 27684889A JP 27684889 A JP27684889 A JP 27684889A JP H03136358 A JPH03136358 A JP H03136358A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- semiconductor chip
- conductors
- semiconductor device
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 239000004020 conductor Substances 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 230000000149 penetrating effect Effects 0.000 claims 1
- 239000012212 insulator Substances 0.000 abstract description 6
- 239000010949 copper Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 238000003466 welding Methods 0.000 abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052802 copper Inorganic materials 0.000 abstract description 3
- -1 polytetrafluoroethylene Polymers 0.000 abstract description 3
- 229920001343 polytetrafluoroethylene Polymers 0.000 abstract description 3
- 239000004810 polytetrafluoroethylene Substances 0.000 abstract description 3
- 229910000679 solder Inorganic materials 0.000 abstract description 3
- 230000005496 eutectics Effects 0.000 abstract description 2
- 229910001111 Fine metal Inorganic materials 0.000 abstract 1
- 229910020220 Pb—Sn Inorganic materials 0.000 abstract 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract 1
- 229910052737 gold Inorganic materials 0.000 abstract 1
- 229910052760 oxygen Inorganic materials 0.000 abstract 1
- 239000001301 oxygen Substances 0.000 abstract 1
- 239000000919 ceramic Substances 0.000 description 21
- 238000007747 plating Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000005219 brazing Methods 0.000 description 3
- 239000006023 eutectic alloy Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000007526 fusion splicing Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000011514 reflex Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は高周波用の半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a high frequency semiconductor device.
従来の高周波半導体装置は、第５図（ａ）。 A conventional high frequency semiconductor device is shown in FIG. 5(a).
（ｂ）に示すように、セラミック基板１の表面にタング
ステンペーストを選択的に印刷してダイ・アタッチ部２
を形成し、セラミック基板１の上にダイ・アタッチ部２
の周囲にセラミック枠３を積層して設け、セラミック枠
３の上面にタングステンペーストを印刷する０次に、セ
ラミック基板１のメタライズ層とセラミック枠３のメタ
ライズ層がスルーホール４又は側面メタライズ層５によ
って接続されている０次に、セラミック枠３のメタライ
ズ層上にセラミック枠６を積層して設け、その上面に放
射状にパターニングされたメタライズ層７を設け、電源
及び信号の入出力の導体とする。このセラミ・レフ枠６
の厚さは極力薄く、例えば、０．１ｍｍ程魔マメタライ
ズ層７の導体幅も極めて細く０．１〜Ｏ０・２龍である
。この様にしてメタライズ層７の導体インピーダンスを
５０Ωになる様に鰻計・製作する−このセラミック枠６
の上には、セラミック基１２を積層して設け、その上面
にタングステンメタライズ層が印刷される。As shown in (b), tungsten paste is selectively printed on the surface of the ceramic substrate 1 to form the die attach area 2.
A die attach section 2 is formed on the ceramic substrate 1.
A ceramic frame 3 is stacked and provided around the ceramic frame 3, and tungsten paste is printed on the top surface of the ceramic frame 3.Next, the metallized layer of the ceramic substrate 1 and the metallized layer of the ceramic frame 3 are formed through the through hole 4 or the side metallized layer 5. Next, a ceramic frame 6 is laminated on the metallized layer of the ceramic frame 3, and a radially patterned metallized layer 7 is provided on the upper surface of the ceramic frame 6 to serve as a conductor for inputting and outputting power and signals. This ceramic reflex frame 6
The thickness of the metallized layer 7 is as thin as possible, for example, about 0.1 mm, and the conductor width of the metallized layer 7 is also extremely thin, ranging from 0.1 to 0.2 mm. In this way, the conductor impedance of the metallized layer 7 is measured and manufactured to be 50Ω - this ceramic frame 6
A ceramic base 12 is laminated thereon, and a tungsten metallization layer is printed on the upper surface thereof.
このメタライズ層並びに他のセラミック基板のメタライ
ズ層にはＮｉめっき層とＡｕめっき層が設けられている
。又外部リード９にも同様にＮｉめっき層とＡｕめっき
層が設けられている。この高周波半導体パッケージのグ
イ・アタッチ部２にＡｕ−３ｔ共晶合金により半導体チ
ップ８を固着し、Ａｕ線又はＡρ線の金属細線１０によ
り半導体チップ８の電極とメタライズ層７とを接続する
。次にキャップ１１とセラミック枠１２との間をＡｕ−
３ｎろう材で融着接続して半導体装置が構成される。This metallized layer and other metallized layers of the ceramic substrate are provided with a Ni plating layer and an Au plating layer. Similarly, the external lead 9 is also provided with a Ni plating layer and an Au plating layer. A semiconductor chip 8 is fixed to the gouging attachment part 2 of this high frequency semiconductor package using an Au-3t eutectic alloy, and the electrodes of the semiconductor chip 8 and the metallized layer 7 are connected by a thin metal wire 10 of Au or Ap wire. Next, between the cap 11 and the ceramic frame 12, Au-
A semiconductor device is constructed by fusion splicing using a 3N brazing filler metal.
上述した従来の高周波半導体装置は、パッケージ内の導
体の特性インピーダンスとプリント配線基板の導体線路
の特性インピーダンスの値が同じになる様に設計製造し
である。（通常は５０Ω）しかしながら、プリント配線
基板の特性インピーダンスに対して、パッケージの特性
インピーダンスはセラミ°ツク内部導体と外部金属リー
ドでインピーダンスの値が異なりこの部分で信号の反射
が発生し信号の減衰の原因となっていた。又、パッケー
ジ内部及び隣接する外部リードは、お互いの信号が相手
側に乗り移る漏話現象が発生し、ノイズの原因又は利得
の低下の原因となっていた。The conventional high-frequency semiconductor device described above is designed and manufactured so that the characteristic impedance of the conductor in the package and the characteristic impedance of the conductor line of the printed wiring board are the same. (Normally 50Ω) However, compared to the characteristic impedance of the printed wiring board, the characteristic impedance of the package differs between the ceramic internal conductor and the external metal lead, and signal reflection occurs in this part, resulting in signal attenuation. It was the cause. Further, a crosstalk phenomenon occurs between the inside of the package and the adjacent external leads, in which signals are transferred to the other side, which causes noise or decreases in gain.
本発明の半導体装置は、箱型の金属容器と、前記金属容
器の内側底面に搭載した半導体チップと、前記金属容器
を貫通して中心導体の先端を前記半導体チップの周囲に
配置して設け且つ前記中心導体と前記半導体チップの電
極との間を電気的に接続し外部導体を前記金属容器に接
合して設けた同軸リードとを備えている。The semiconductor device of the present invention includes a box-shaped metal container, a semiconductor chip mounted on the inner bottom surface of the metal container, and a center conductor that extends through the metal container with a tip thereof arranged around the semiconductor chip. A coaxial lead is provided to electrically connect the center conductor and the electrode of the semiconductor chip, and an outer conductor is connected to the metal container.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（Ｃ）は本発明の第１の実施例の製造方
法を説明するための工程順に示した半導体装置の断面図
である。FIGS. 1A to 1C are cross-sectional views of a semiconductor device shown in the order of steps for explaining the manufacturing method of the first embodiment of the present invention.
まず、第１図（ａ）に示すように、コバール合金、４２
合金、Ｃｕ−Ｗ又はＣｕの複合合金からなる金属板を切
削加工又は打抜き・プレス加工して箱型の容器１３を形
成し、容器１３の側壁１４に貫通孔１６を設ける０次に
、容器１３の内側底面の中央部に半導体チップ８をＡｕ
−３ｉ共晶合金からなるろう材により接合する。First, as shown in FIG. 1(a), Kovar alloy, 42
A box-shaped container 13 is formed by cutting or punching/pressing a metal plate made of alloy, Cu-W, or Cu composite alloy, and a through hole 16 is provided in the side wall 14 of the container 13. The semiconductor chip 8 is placed in the center of the inner bottom surface of the Au
-3i A brazing material made of eutectic alloy is used for joining.
次に、第１図（ｂ）に示すように、直径０゜３７ｍｍの
銅被覆鋼線の表面に銀めっき層を設けた中心導体１８と
直径１−２４ｍ＋＋ａのポリテトラフルオロエチレンか
らなる絶縁体１９と、直径１．６ｍｍのシームレス無酸
素銅バイブからなる外部導体１５とからなり５０〜７５
Ωの特性インピーダンスを有するセミ・リジットな同軸
リード１７を貫通孔１６に挿入し、半導体チップ８の周
囲に中心導体１８の先端部を配置するようにして貫通孔
１６の側壁１４と外部導体１５をｐｂ−Ｓｎ共晶半田２
４で接合する。Next, as shown in FIG. 1(b), a central conductor 18 made of a copper-coated steel wire with a diameter of 0°37 mm and a silver plating layer provided on the surface, and an insulator 19 made of polytetrafluoroethylene with a diameter of 1-24 m++a. and an outer conductor 15 made of a seamless oxygen-free copper vibe with a diameter of 1.6 mm.
A semi-rigid coaxial lead 17 having a characteristic impedance of Ω is inserted into the through hole 16, and the side wall 14 of the through hole 16 and the outer conductor 15 are connected so that the tip of the center conductor 18 is placed around the semiconductor chip 8. pb-Sn eutectic solder 2
Join with 4.
次に、第１図（ｃ）に示すように、半導体チップ８の電
極と中心導体１８の先端部との間をＡｕ線又はＡｆｆｌ
線からなる金属細線１０によりワイヤーボンディングし
て接続する。この場合、金属細線の長さは最短共になる
様に接続する。この時の金属細線１０の長さを０，５韻
以下にすると金属細線１０のインダクタンスは、０．４
〜０．５ｎＨに相当する。次に、半導体チップ８の保護
のために金属キャップ２０をシームウェルド法により気
密封止する。シームウェルド法による封止は、封止時の
発熱が極めて低く抑えられるので同軸り・−ド１７の半
田付部とセミリジット同軸ケーブルのポリテトラフルオ
ロエチレンからなる絶縁体１９に与えるダメージを最少
限に抑えることができる。同軸リード１７の外側先端部
の中心導体１８が１〜２ ａｍ露出する様に絶縁体１９
及び外部導体１５を除去する。Next, as shown in FIG. 1(c), an Au wire or an Affl wire is connected between the electrode of the semiconductor chip 8 and the tip of the center conductor 18.
The connection is made by wire bonding using a thin metal wire 10 made of wire. In this case, the thin metal wires are connected so that their lengths are the shortest. At this time, if the length of the thin metal wire 10 is set to 0.5 rhymes or less, the inductance of the thin metal wire 10 is 0.4
Corresponds to ~0.5 nH. Next, to protect the semiconductor chip 8, the metal cap 20 is hermetically sealed by seam welding. Sealing by the seam welding method suppresses heat generation during sealing to an extremely low level, minimizing damage to the soldered part of the coaxial cable 17 and the insulator 19 made of polytetrafluoroethylene of the semi-rigid coaxial cable. It can be suppressed. The insulator 19 is placed so that the center conductor 18 at the outer tip of the coaxial lead 17 is exposed for 1 to 2 am.
and remove the outer conductor 15.
第２図は本発明の半導体装置の実装状態を示す斜視図で
あり、キャップを外した状態を示す。FIG. 2 is a perspective view showing the mounted state of the semiconductor device of the present invention, with the cap removed.
同軸リード１７の中心導体１８を５０Ωの特性インピー
ダンスにマツチングされた回路を有するプリント配線基
板２１のランド２２に挿入し半田付けし、プリント配線
基板２１の回路と接続する。The center conductor 18 of the coaxial lead 17 is inserted into the land 22 of the printed wiring board 21 having a circuit matched to a characteristic impedance of 50Ω, soldered, and connected to the circuit of the printed wiring board 21.
なお、同軸リード１７は、絶縁体１９にセラミックを用
いたリジット同軸リードを用いても良い。Note that the coaxial lead 17 may be a rigid coaxial lead in which the insulator 19 is made of ceramic.
第３図（ａ）、（ｂ）は本発明の第２の実施例を説明す
るための工程順に示した半導体装置の断面図である。FIGS. 3(a) and 3(b) are cross-sectional views of a semiconductor device shown in order of steps for explaining a second embodiment of the present invention.
第３図（ａ）に示すように、第１図（ａ）により説明し
た第１の実施例と同様に側壁１４に貫通孔１６を設けた
箱型の容器１３の内側底面に半導体チップ８をＡｕ−３
ｉ共晶合金を用いて固着する。次に、容器１３の貫通孔
１６に中心導体１８の先端を露出された同軸リード１７
を挿入し、中心導体１８を半導体チップ８の電極の真上
に位置するようにして貫通孔１６と同軸リード１７の外
部導体１５を半田の様な低融点ろう材で接続する。As shown in FIG. 3(a), a semiconductor chip 8 is placed on the inner bottom surface of a box-shaped container 13 having a through hole 16 in the side wall 14, similar to the first embodiment described in FIG. 1(a). Au-3
i Fix using a eutectic alloy. Next, the coaxial lead 17 with the tip of the center conductor 18 exposed in the through hole 16 of the container 13
is inserted, the center conductor 18 is positioned directly above the electrode of the semiconductor chip 8, and the through hole 16 and the outer conductor 15 of the coaxial lead 17 are connected with a low melting point brazing material such as solder.
次に、第３図（ｂ）に示すように、中心導体１８の先端
と半導体チップ８の電極を超音波又は熱圧着により、加
圧接続する０次に、電極と中心導体１８の接続状態を確
認後半導体チップ８の表面の吸着水分をオーブンで加熱
放散させてから金属キャップ２０をシームウェルド法に
より容器１３に溶接して封止する。Next, as shown in FIG. 3(b), the tip of the center conductor 18 and the electrode of the semiconductor chip 8 are connected under pressure by ultrasonic or thermocompression bonding. After confirmation, the moisture adsorbed on the surface of the semiconductor chip 8 is heated and dissipated in an oven, and then the metal cap 20 is welded to the container 13 by a seam welding method to seal it.
第４図（ａ）、（ｂ）は本発明の第３の実施例を示す切
欠平面図及びＡ−Ａ’線断面図である。FIGS. 4(a) and 4(b) are a cutaway plan view and a sectional view taken along the line AA', showing a third embodiment of the present invention.
同軸リード１７を容器１３の底部を貫通して設けた以外
は第１の実施例と同じ構成を有している。This embodiment has the same structure as the first embodiment except that the coaxial lead 17 is provided through the bottom of the container 13.
以上説明した様に本発明は、容器とキャップを金属で形
成し、電源ならび信号用導体に同軸ケーブルを用いてい
る。従って導体のインピーダンス整合は５０Ω又は７５
Ωに確実に設定できプリント配線基板のインピーダンス
に合わせることができる。又パッケージ全体が金属でつ
くられているので充分な接地ができ隣接信号ピンの信号
の漏話を防止できるという効果を有する。As explained above, in the present invention, the container and the cap are made of metal, and a coaxial cable is used as the power supply and signal conductor. Therefore, the impedance matching of the conductor is 50Ω or 75Ω.
It can be reliably set to Ω and matched to the impedance of the printed wiring board. Furthermore, since the entire package is made of metal, sufficient grounding can be achieved and crosstalk of signals from adjacent signal pins can be prevented.
また、実装時の半導体チップの電極部及びプリント配線
基板のランドと中心導体の接続部の反射によるインピー
ダンス不整合を最小に抑えて半導体を実装した回路の高
周波特性を向上できるという効果を有する。Furthermore, impedance mismatching caused by reflections between the electrode portion of the semiconductor chip and the connecting portion between the land of the printed wiring board and the center conductor during mounting can be minimized, thereby improving the high frequency characteristics of the circuit in which the semiconductor is mounted.
第１図（ａ）〜（ｃ）は本発明の第１の実施例の製造方
法を説明するための半導体装置の断面図、第２図は本発
明の半導体装置の実装状態を示す斜視図、第３図（ａ）
、（ｂ）は本発明の第２の実施例を説明す・るための工
程順に示した半導体装置の断面図、第４図（ａ）、（ｂ
）は本発明の第３の実施例を示す切欠平面図及びＡ−Ａ
’線断面図、第５図（ａ）、（ｂ）は従来の半導体装置
の斜視図及び断面図である。
１・・・セラミック基板、２・・・グイ・アタッチ部、
３・・・セラミック枠、４・・・スルーホール、５・・
・側面メタライズ層、６・・・セラミック枠、７・・・
メタライズ層、８・・・半導体チップ、９・・・外部リ
ード、１０・・・金属細線、１１・・・キャップ、１２
・・・セラミック枠、１３・・・容器、１４・・・側壁
、１５・・・外部導体、１６・・・貫通孔、１７・・・
同軸リード、１８・・・中心導体、９・・・絶縁体、２
０・・・金属キャップ、２１−・・プリント配線基板、
２２・・・ランド、２４・・・半田。1(a) to (c) are cross-sectional views of a semiconductor device for explaining the manufacturing method of the first embodiment of the present invention, FIG. 2 is a perspective view showing the mounting state of the semiconductor device of the present invention, Figure 3(a)
, (b) are cross-sectional views of a semiconductor device shown in the order of steps for explaining the second embodiment of the present invention, and FIGS.
) is a cutaway plan view showing the third embodiment of the present invention and A-A
Figures 5(a) and 5(b) are a perspective view and a sectional view of a conventional semiconductor device. 1... Ceramic board, 2... Gui attachment part,
3...Ceramic frame, 4...Through hole, 5...
・Side metallized layer, 6...Ceramic frame, 7...
Metallized layer, 8... Semiconductor chip, 9... External lead, 10... Metal thin wire, 11... Cap, 12
...Ceramic frame, 13...Container, 14...Side wall, 15...Outer conductor, 16...Through hole, 17...
Coaxial lead, 18... Center conductor, 9... Insulator, 2
0...Metal cap, 21-...Printed wiring board,
22...land, 24...handa.
Claims (1)
た半導体チップと、前記金属容器を貫通して中心導体の
先端を前記半導体チップの周囲に配置して設け且つ前記
中心導体と前記半導体チップの電極との間を電気的に接
続し外部導体を前記金属容器に接合して設けた同軸リー
ドとを備えたことを特徴とする半導体装置。a box-shaped metal container; a semiconductor chip mounted on the inner bottom surface of the metal container; a center conductor penetrating through the metal container with a tip of the center conductor disposed around the semiconductor chip; and the center conductor and the semiconductor chip. 1. A semiconductor device comprising: a coaxial lead electrically connected to an electrode of the metal container and having an outer conductor bonded to the metal container.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27684889A JPH03136358A (en) | 1989-10-23 | 1989-10-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27684889A JPH03136358A (en) | 1989-10-23 | 1989-10-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03136358A true JPH03136358A (en) | 1991-06-11 |
Family
ID=17575252
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27684889A Pending JPH03136358A (en) | 1989-10-23 | 1989-10-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03136358A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04368165A (en) * | 1991-06-17 | 1992-12-21 | Nec Yamagata Ltd | Package for semiconductor device |
| US5783857A (en) * | 1996-07-25 | 1998-07-21 | The Whitaker Corporation | Integrated circuit package |
| JP2010286411A (en) * | 2009-06-12 | 2010-12-24 | Denso Corp | Capacitive occupant sensor |
-
1989
- 1989-10-23 JP JP27684889A patent/JPH03136358A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04368165A (en) * | 1991-06-17 | 1992-12-21 | Nec Yamagata Ltd | Package for semiconductor device |
| US5783857A (en) * | 1996-07-25 | 1998-07-21 | The Whitaker Corporation | Integrated circuit package |
| JP2010286411A (en) * | 2009-06-12 | 2010-12-24 | Denso Corp | Capacitive occupant sensor |
| US8294478B2 (en) | 2009-06-12 | 2012-10-23 | Denso Corporation | Capacitive occupant sensor |
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