JPH03135043A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH03135043A JPH03135043A JP27160589A JP27160589A JPH03135043A JP H03135043 A JPH03135043 A JP H03135043A JP 27160589 A JP27160589 A JP 27160589A JP 27160589 A JP27160589 A JP 27160589A JP H03135043 A JPH03135043 A JP H03135043A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- power supply
- insulating sheet
- power
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 229910000679 solder Inorganic materials 0.000 abstract description 5
- 238000000605 extraction Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000012790 confirmation Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電源ノイズを低減できるフィルムキャリア方
式の半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a film carrier type semiconductor integrated circuit that can reduce power supply noise.
従来、フィルムキャリア方式の半導体集積回路の電源ノ
イズ低減方法については、電子材料（１９８９年７月）
２７頁から３１頁に記載のように、絶縁シートの上面に
信号パターンを形成し、下面にグランドパターンを形成
し、集積回路のグランド端子をインナーリード近くでス
ルホールを経由して下面のグランドパターンに接続する
ことにより行なっていた。Conventional methods for reducing power supply noise in film carrier type semiconductor integrated circuits are described in Electronic Materials (July 1989).
As described on pages 27 to 31, a signal pattern is formed on the top surface of the insulating sheet, a ground pattern is formed on the bottom surface, and the ground terminal of the integrated circuit is connected to the ground pattern on the bottom surface via a through hole near the inner lead. This was done by connecting.
上記従来技術は、フィルムキャリアが多層構造であり、
かつスルホールを形成する必要があり、製造工程が複雑
でコスト高となる問題があった。In the above conventional technology, the film carrier has a multilayer structure,
In addition, it is necessary to form through holes, resulting in a complicated manufacturing process and high cost.
本発明の目的は、製造工程が簡単で製造コストが安く、
しかも電源ノイズを低減できるフィルムキャリア方式の
半導体集積回路を提供することにある。The purpose of the present invention is to have a simple manufacturing process, low manufacturing cost,
Moreover, it is an object of the present invention to provide a film carrier type semiconductor integrated circuit that can reduce power supply noise.
更に本発明の目的は、信号端子を減少させることなく電
源ノイズを低減できる半導体集積回路を提供することに
ある。A further object of the present invention is to provide a semiconductor integrated circuit that can reduce power supply noise without reducing the number of signal terminals.
上記目的を達成するために、集積回路素子の外周部と絶
縁シートの外周部の間の絶縁シート部分に電源用アウタ
ーリードを配置したものである。In order to achieve the above object, an outer lead for a power supply is arranged in a portion of an insulating sheet between an outer periphery of an integrated circuit element and an outer periphery of an insulating sheet.
更に上記目的を達成するために、電源用アウターリード
の形状をピン形にしたものである。Furthermore, in order to achieve the above object, the shape of the power supply outer lead is made into a pin shape.
上記他の目的を達成するために、電源用インナーリード
を集積回路素子のコーナー部に配置し。In order to achieve the other objects mentioned above, inner leads for power supply are arranged at the corners of the integrated circuit element.
集積回路素子のコーナーと絶縁シートのコーナーとの間
の絶縁シート部分に、電源用アウターリードを配置した
ものである。A power supply outer lead is arranged in the insulating sheet portion between the corner of the integrated circuit element and the corner of the insulating sheet.
集積回路素子の外周部と絶縁シートの外周部との間の絶
縁シート部分に電源用アウターリードを設置することに
より、集積回路素子の電源端子から７ウターリードまで
の配線長が短くなり、電源インピーダンスを下げ電源ノ
イズを低減することができる。By installing the power supply outer lead on the insulating sheet between the outer periphery of the integrated circuit element and the outer periphery of the insulation sheet, the wiring length from the integrated circuit element's power supply terminal to the 7th outer lead is shortened, reducing the power supply impedance. Lowering power supply noise can be reduced.
電源用アウターリードの形状をピン形にすることにより
、従来と同じくスルホールを形成することにはなるが、
プリント基板の電源内層と直接接続可能となり、電源イ
ンピーダンスを下げ電源ノイズを低減することができる
。By changing the shape of the power supply outer lead to a pin shape, a through hole will be formed as in the past, but
It can be directly connected to the power supply inner layer of the printed circuit board, lowering power supply impedance and reducing power supply noise.
以下、本発明の一実施例を第１図および第２図により説
明する。An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.
第１図は、本発明の一実施例であるフィルムキャリア方
式の半導体集積回路の平面図、第２図は、第１図のＡ−
Ａ’断面でプリント基板と接続している図である。FIG. 1 is a plan view of a film carrier type semiconductor integrated circuit which is an embodiment of the present invention, and FIG.
It is a diagram showing connection with a printed circuit board at A' cross section.
ポリイミドフィルム等から成る絶縁シート１上に配線パ
ターン７およびインナーリード３．アウターリート４が
形成されている。インナーリード３は、集積回路素子２
にＣＣＢ （ＣｏｎｆｒｏｌｌｅｄＣｏｌａｐｓｅ
Ｂ ｏｎｄｉｎｇ）技術により一括ハンダ接続される。A wiring pattern 7 and inner leads 3 are formed on an insulating sheet 1 made of polyimide film or the like. An outer reel 4 is formed. The inner lead 3 is connected to the integrated circuit element 2
CCB (Confrolled Collapse)
They are soldered together using bonding technology.
アウターリード４は一プリント基板２０のパッド２１に
ハンダ１０等により接続される。The outer lead 4 is connected to a pad 21 of a printed circuit board 20 with solder 10 or the like.
ここで、電源用アウターリード５は、絶縁シート１の集
積回路素子２の外周部と絶縁シート１の外周部の間に設
けられた開口部６の所に形成される。Here, the power supply outer lead 5 is formed at an opening 6 provided between the outer periphery of the integrated circuit element 2 of the insulating sheet 1 and the outer periphery of the insulating sheet 1 .
通常は、第２図のように図の上の面でプリント基板２０
のパッド２１と接続するが、下面で接続しても何ら問題
はない。本実施例によれば、電源引き出し線を短くでき
るため、電源インピーダンスを下げ電源ノイズが低減で
きる効果がある。また、集積回路素子に近い点でプリン
ト基板と接続できるため、半導体集積回路のプリント基
板への接続強度が強くなる効果もある。また、開口部６
を設けることで、単に面付けするよりもアウターリード
を包み込む様にしっかりとハンダ付けすることができ、
事後確認、検査も容易に行うことができる。Normally, as shown in Figure 2, the printed circuit board 20 is
However, there is no problem if the connection is made on the bottom surface. According to this embodiment, since the power lead-out line can be shortened, the power supply impedance can be lowered and power supply noise can be reduced. Furthermore, since the semiconductor integrated circuit can be connected to the printed circuit board at a point close to the integrated circuit element, the strength of the connection between the semiconductor integrated circuit and the printed circuit board can be increased. In addition, the opening 6
By providing this, it is possible to firmly solder the outer lead so as to wrap it around it, rather than simply attaching it.
Post-confirmation and inspection can also be easily performed.
第３図は、本発明の他の実施例である。電源用アウター
リード部分にスルホール８を形成し、リードピン９を埋
込み半田１０により接続させたものである。本実施例に
よれば、電源端子がプリント基板の電源内層と直接接続
できるため、さらに電源インピーダンスを下げ電源ノイ
ズを低減することが可能となる。FIG. 3 is another embodiment of the invention. A through hole 8 is formed in the outer lead portion for the power supply, and a lead pin 9 is connected by embedded solder 10. According to this embodiment, since the power supply terminal can be directly connected to the power supply inner layer of the printed circuit board, it is possible to further lower the power supply impedance and reduce power supply noise.
第４図は、本発明の更に他の実施例である。集積回路素
子２の電源端子がコーナ部に配置されており電源用イン
ナーリード３′と接続され、幅の広い電源配線パターン
７′を介して電源用アウターリード５が集積回路素子２
のコーナー部と絶縁シート１のコーナ部との間に形成さ
れている。電源用アウターリード５の部分の絶縁シート
ｌには、開口部６が形成されている。本実施例によれば
信号用配線エリアを小さくすることなく電源配線を引き
出すことができるため、信号端子の減少を防ぐことがで
きる。また、電源配線パターンの幅を大きくできるため
、電源ノイズ低減にも効果がある。FIG. 4 shows yet another embodiment of the invention. The power supply terminal of the integrated circuit element 2 is arranged at the corner and is connected to the power supply inner lead 3', and the power supply outer lead 5 is connected to the integrated circuit element 2 via the wide power supply wiring pattern 7'.
is formed between the corner portion of the insulating sheet 1 and the corner portion of the insulating sheet 1. An opening 6 is formed in the insulating sheet l in the portion of the power supply outer lead 5. According to this embodiment, the power supply wiring can be drawn out without reducing the signal wiring area, so that it is possible to prevent the number of signal terminals from decreasing. Furthermore, since the width of the power supply wiring pattern can be increased, it is also effective in reducing power supply noise.
本発明によれば、電源配線を短くできるため、電源イン
ピーダンスを下げ、電源ノイズを低減できる効果がある
。また、製造方法も容易であり製造コストを安価にでき
る効果もある。According to the present invention, since the power supply wiring can be shortened, the power supply impedance can be lowered and power supply noise can be reduced. Further, the manufacturing method is easy, and the manufacturing cost can be reduced.
第１図は本発明の一実施例の半導体集積回路の平面図５
第２図は、第１図のＡ−Ａ’断面図、第３図は、他の実
施例の断面図、第４図は、更に他の実施例の平面図であ
る。
１・・・絶縁シート、２・・・集積回路素子、３，３′
・・・インナーリード、４・・・アウターリード、５・
・・電源用アウターリード、６・・・開口部、７，７′
・・・配線パターン、８・・・スルホール、９・・・リ
ードピン、１０・・・半田、２０・・・プリント基板、
２１・・・パッド。FIG. 1 is a plan view 5 of a semiconductor integrated circuit according to an embodiment of the present invention.
2 is a sectional view taken along the line AA' in FIG. 1, FIG. 3 is a sectional view of another embodiment, and FIG. 4 is a plan view of still another embodiment. 1... Insulating sheet, 2... Integrated circuit element, 3, 3'
... Inner lead, 4... Outer lead, 5.
... Outer lead for power supply, 6... Opening, 7, 7'
...Wiring pattern, 8...Through hole, 9...Lead pin, 10...Solder, 20...Printed circuit board,
21...Pad.
Claims (1)
ード部分と、プリント基板と接続するアウターリード部
分と、絶縁シート上に形成された導体パターンより成る
フィルムキャリア方式の半導体集積回路において、電源
用アウターリードが集積回路素子の外周部と絶縁シート
の外周部との間に配置されていることを特徴とする半導
体集積回路。 ２、請求項１において、電源用インナーリードを集積回
路素子のコーナ部に配置し、集積回路素子のコーナー部
と絶縁シートのコーナ部との間に電源用アウターリード
を配置したことを特徴とする半導体集積回路。 ３、請求項１、請求項２において、電源用アウターリー
ドの形状がピン形になっていることを特徴とする半導体
集積回路。[Claims] 1. A film carrier type semiconductor integrated circuit comprising an inner lead portion connected to an external output terminal of an integrated circuit element, an outer lead portion connected to a printed circuit board, and a conductive pattern formed on an insulating sheet. 1. A semiconductor integrated circuit, wherein a power supply outer lead is disposed between an outer periphery of an integrated circuit element and an outer periphery of an insulating sheet. 2. In claim 1, the inner lead for power supply is arranged at the corner part of the integrated circuit element, and the outer lead for power supply is arranged between the corner part of the integrated circuit element and the corner part of the insulating sheet. Semiconductor integrated circuit. 3. The semiconductor integrated circuit according to claim 1 or claim 2, wherein the power supply outer lead has a pin shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27160589A JPH03135043A (en) | 1989-10-20 | 1989-10-20 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27160589A JPH03135043A (en) | 1989-10-20 | 1989-10-20 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03135043A true JPH03135043A (en) | 1991-06-10 |
Family
ID=17502406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27160589A Pending JPH03135043A (en) | 1989-10-20 | 1989-10-20 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03135043A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6734545B1 (en) | 1995-11-29 | 2004-05-11 | Hitachi, Ltd. | BGA type semiconductor device and electronic equipment using the same |
-
1989
- 1989-10-20 JP JP27160589A patent/JPH03135043A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6734545B1 (en) | 1995-11-29 | 2004-05-11 | Hitachi, Ltd. | BGA type semiconductor device and electronic equipment using the same |
| US7164194B2 (en) | 1995-11-29 | 2007-01-16 | Renesas Technology Corp. | BGA type semiconductor device and electronic equipment using the same |
| US7291909B2 (en) | 1995-11-29 | 2007-11-06 | Renesas Technology Corp. | BGA type semiconductor device and electronic equipment using the same |
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