JP3269506B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP3269506B2
JP3269506B2 JP03639793A JP3639793A JP3269506B2 JP 3269506 B2 JP3269506 B2 JP 3269506B2 JP 03639793 A JP03639793 A JP 03639793A JP 3639793 A JP3639793 A JP 3639793A JP 3269506 B2 JP3269506 B2 JP 3269506B2
Authority
JP
Japan
Prior art keywords
conductive
land
semiconductor device
pellet
electrode pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP03639793A
Other languages
Japanese (ja)
Other versions
JPH06252205A (en
Inventor
勲 野瀬
Original Assignee
関西日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 関西日本電気株式会社 filed Critical 関西日本電気株式会社
Priority to JP03639793A priority Critical patent/JP3269506B2/en
Publication of JPH06252205A publication Critical patent/JPH06252205A/en
Application granted granted Critical
Publication of JP3269506B2 publication Critical patent/JP3269506B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、絶縁シート上に形成し
た導電パターンと半導体ペレットとを電気的接続した半
導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a conductive pattern formed on an insulating sheet and a semiconductor pellet are electrically connected.

【0002】[0002]

【従来の技術】TAB式半導体装置は、例えばフレキシ
ブルなシート状プリント基板等に組み付けられるカメラ
用IC等に用いられ、その一例を図4及び図5を参照し
て次に示すと、(1)は半導体ペレット(以下、ペレッ
トと称す。)、(2)は枠状シート、(3)は金属箔リ
ードである。そして、金属箔リード(3)を枠状シート
(2)の内側から外側に向って放射状に配置すると共
に、その中間部分を枠状シート(2)に接着し、且つ、
ペレット(1)の表面外周縁に金メッキにより形成した
バンプ電極(4)…とインナーリード(3a)とを熱圧
着してボンディングすることによりペレット(1)を枠
状シート(2)の内側に支持する。
2. Description of the Related Art A TAB type semiconductor device is used, for example, in a camera IC or the like assembled on a flexible sheet-like printed circuit board or the like, and an example thereof is shown below with reference to FIGS. Denotes a semiconductor pellet (hereinafter, referred to as a pellet), (2) denotes a frame-shaped sheet, and (3) denotes a metal foil lead. Then, the metal foil leads (3) are radially arranged from the inside to the outside of the frame-shaped sheet (2), and an intermediate portion thereof is bonded to the frame-shaped sheet (2), and
A bump electrode (4) formed by gold plating on the outer peripheral edge of the surface of the pellet (1) and an inner lead (3a) are bonded by thermocompression bonding to support the pellet (1) inside the frame-shaped sheet (2). I do.

【0003】上記TAB式半導体装置(5)は、図5に
示すように、TABテープ(6)を所定のピッチと形状
で切断したものからなり、TABテープ(6)は、透孔
(7)…と窓開け部(8)…と送り穴(9)…とを有す
る長尺な絶縁シート(10)の表面に所定パターンの金
属箔リード(3)を被着・形成すると共に、透孔(7)
内においてバンプ電極(4)…とインナーリード(3
a)とを熱圧着ボンディングすることによりペレット
(1)を透孔(7)内に支持してなる。
As shown in FIG. 5, the TAB type semiconductor device (5) is formed by cutting a TAB tape (6) at a predetermined pitch and shape. The TAB tape (6) has a through hole (7). , A window opening (8), and a perforation hole (9), a metal foil lead (3) having a predetermined pattern is attached and formed on the surface of a long insulating sheet (10). 7)
Inside the bump electrode (4) ... and the inner lead (3)
The pellet (1) is supported in the through hole (7) by thermocompression bonding of (a).

【0004】[0004]

【発明が解決しようとする課題】解決しようとする課題
は、TAB式半導体装置において、多ピン化により電極
数及びリード本数が多くなると、バンプ電極(4)…を
ペレット表面外周縁に沿って各辺毎に直線上に配置して
いるため、まず電極サイズ及び電極間ピッチをそれぞれ
小さくし、それに伴ってリード(3)も細く薄く、且
つ、リード間ピッチも狭くする必要があり、その結果、
リードを長く成形することが困難で、又、ボンディング
不良やリード変形、短絡が生じ易くなって、多ピン化に
限界があり、多ピン化してもリードの機械的強度が弱く
て取り扱いが困難で、組立性も低下する点である。そこ
で、従来、バンプ電極(4)…を千鳥足状に配置したも
のもあるが、リード(3)は依然として細く薄く、且
つ、リード間ピッチも狭くなるため、同様に多ピン化に
限界があり、組立性も低下する。
The problem to be solved is that, in a TAB type semiconductor device, when the number of electrodes and the number of leads increase due to the increase in the number of pins, bump electrodes (4). Since the electrodes are arranged on a straight line for each side, it is necessary to first reduce the electrode size and the pitch between the electrodes, and accordingly, the leads (3) must be thin and thin, and the pitch between the leads must be narrow.
It is difficult to form long leads, and it is easy to cause bonding failure, lead deformation, and short circuit, and there is a limit to increasing the number of pins. Also, the assemblability is reduced. Conventionally, bump electrodes (4) are arranged in a zigzag pattern, but the leads (3) are still thin and thin, and the pitch between the leads is narrow. The assemblability also decreases.

【0005】[0005]

【課題を解決するための手段】本発明は、上面にほぼ平
坦な電極パッドを多数形成し、電極パッド形成領域より
外方位置に位置確認マークを形成した半導体ペレット
と、一方の面に導電パターンを、他の面の上記電極パッ
ドと対応する位置に導電ランドをそれぞれ形成し、他の
面の導電ランドとその近傍を除く部分をエッチングして
部分的に肉薄に形成し導電パターン及び導電ランドを透
孔を介して電気的接続すると共に、半導体ペレットの位
置確認マークと対応する位置に位置確認孔を設け、半導
体ペレットの電極パッドと導電ランドが電気的に接続さ
れる絶縁シートとを具備したことを特徴とする。
According to the present invention, an almost flat surface is provided on an upper surface.
Forming a large number of flat electrode pads, from the electrode pad formation area
Semiconductor pellet with a position confirmation mark formed at the outer position
And a conductive pattern on one side, and the electrode pads on the other side.
Conductive lands are formed at positions corresponding to the
Etching the surface except the conductive land and its vicinity
Partially formed thin and transparent through conductive patterns and conductive lands
Electrical connection through the hole and the position of the semiconductor pellet
A position confirmation hole is provided at the position corresponding to the
The electrode pads of the body pellet and the conductive lands are electrically connected.
And an insulating sheet .

【0006】[0006]

【作用】上記技術的手段によれば、絶縁シートの一方の
面に形成した導電パターンと他方の面に形成した導電ラ
ンドとを透孔を介して電気的接続し、上記導電ランドに
ペレット電極パッドを重ねて電気的接続すると、電極配
置パターン任意に形成出来、且つ、リード本数が多い半
導体装置を得る。
According to the above technical means, the conductive pattern formed on one surface of the insulating sheet and the conductive land formed on the other surface are electrically connected to each other through the through hole, and the conductive land is connected to the pellet electrode pad. Are electrically connected to each other, an electrode arrangement pattern can be arbitrarily formed, and a semiconductor device having a large number of leads is obtained.

【0007】[0007]

【実施例】本発明に係る半導体装置の実施例を図1乃至
図3を参照して以下に説明する。まず図1(a)(b)
において、(11)は絶縁シート、(12)はペレッ
ト。(13)は貫通孔である。上記絶縁シート(11)
は各所定位置に位置確認孔(13)と送り穴(14)・
・・を適正な配線パターンで引き回してなる導電パター
ン(16)を形成すると共に、裏面に導電ランド(1
7)を形成し、内周面に導電層(18a)を形成した表
裏貫通の透孔(18)・・・を介して導電パターン(1
6)と導電ランド(17)とを電気的接続してなる。そ
して図1(b)に示すように、裏面をエッチングにより
導電ランド(17)とその近傍を除いて厚さ(d)だけ
部分的肉薄に形成して導電ランド(17)を局所的に突
出させる。ここで、上記透孔(18)・・・はその内周
面に金属メッキ等にて導電層(18a)を被着形成する
と共に、絶縁シート(11)に後述するペレット(1
2)の電極パッド形成パターンと同じパターンで配置す
る。ペレット(12)は、上面に任意パターンで配置・
形成したフラットな電極パッド(19)・・・と十字状
位置マーク(M)[図1(a)参照]を有し、電極パッ
ド(19)を絶縁シート(11)の裏面側から各導電ラ
ンド(17)・・・に熱圧着等にて電気的接続する。
置マーク(M)は図示例では半導体ペレット(12)の
四隅の電極パッド形成領域の外方に形成され、絶縁シー
ト(11)の貫通孔(13)のうち、位置確認孔は位置
マーク(M)に対応して配置される。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device according to the present invention will be described below with reference to FIGS. First, FIGS. 1 (a) and 1 (b)
, (11) is an insulating sheet, and (12) is a pellet. (13) is a through hole. The insulating sheet (11)
Indicates the position confirmation holes (13) and feed holes (14)
.. forming a conductive pattern (16) formed by routing the wiring with an appropriate wiring pattern, and a conductive land (1) on the back surface.
7), and a conductive pattern (1) is formed through a through hole (18) penetrating the front and back sides on which a conductive layer (18a) is formed on the inner peripheral surface.
6) and the conductive land (17) are electrically connected. Then, as shown in FIG. 1B, the back surface is partially thinned by the thickness (d) except for the conductive land (17) and its vicinity by etching to locally project the conductive land (17). . Here, a conductive layer (18a) is formed on the inner peripheral surface of the through hole (18) by metal plating or the like, and a pellet (1) to be described later is formed on the insulating sheet (11).
They are arranged in the same pattern as the electrode pad formation pattern in 2). The pellets (12) are arranged in an arbitrary pattern on the upper surface.
Formed flat electrode pads (19) and cross-shaped position marks (M) [see FIG. 1 (a)]. (17) ... are electrically connected by thermocompression bonding or the like. Rank
The placement mark (M) indicates the semiconductor pellet (12) in the illustrated example.
Formed outside the four corner electrode pad formation areas,
Of the through holes (13) of (g)
It is arranged corresponding to the mark (M).

【0008】上記構成に基づき本発明の動作を次に説明
する。まずボンディングステージ(図示せず)上にペレ
ット(12)を位置決め載置して加熱してシート下方に
配する。且つ、シート上方から目視して位置確認孔(1
3)に位置マーク(M)を合わせ、電極パッド(19)
…と導電ランド(17)…との重ね位置を確認する。そ
こで、局所的に突出した導電ランド(17)…を電極パ
ッド(19)…に重ねて密着させてシート上方からキャ
ピラリ等にて加圧・熱圧着し、両者を電気的接続する。
そうすると、リード本数及び電極数が多くても、それに
伴って適宜、絶縁シート上における導電パターン(1
6)及びペレット上面における電極パッド(19)…を
それぞれ任意の配置パターンで設定すれば良く、同時
に、リード間ピッチも拡げることが出来る。
Next, the operation of the present invention based on the above configuration will be described. First, the pellet (12) is positioned and mounted on a bonding stage (not shown), heated and arranged below the sheet. In addition, the position confirmation holes (1
3) Align the position mark (M) with the electrode pad (19)
And the conductive lands (17) are checked for overlapping positions. Therefore, the locally protruding conductive lands (17) are overlapped on and closely adhered to the electrode pads (19), and are pressurized and thermocompressed with a capillary or the like from above the sheet to electrically connect them.
Then, even if the number of leads and the number of electrodes are large, the conductive pattern (1
6) and the electrode pads (19) on the upper surface of the pellet may be set in any arrangement pattern, and at the same time, the pitch between leads can be increased.

【0009】次に、本発明の他の実施例を図2及び図3
(a)(b)を参照して示すと、相違する点は、それぞ
れ導電ランド(20)(21)の構造で、まず図2に示
す実施例では、絶縁シート(11)の透孔(22)の内
周面に金属メッキ等にて導電層(22a)を被着形成す
ると共に、孔内に半田等の金属(23)を充填して絶縁
シート裏面の導電ランド(20)側に凸状に突出させ
る。そこで、絶縁シート表面の導電パターン(16)と
導電ランド(20)とを透孔(22)を介して電気的接
続し、ペレット(12)の電極パッド(19)と導電ラ
ンド(20)とを重ねて加圧・熱圧着にて電気的接続す
ると、充填金属(23)も接続されて圧着面積が大きく
なり、電気的、且つ、機械的接続強度が増大する。又、
圧着面積が増大した分、透孔径を小さく出来るため、電
極配列ピッチを更に小さくして電極数及びリード本数を
増やすことが出来る。
Next, another embodiment of the present invention will be described with reference to FIGS.
2 (a) and 2 (b), the difference is the structure of the conductive lands (20) and (21). In the embodiment shown in FIG. ), A conductive layer (22a) is adhered to the inner peripheral surface by metal plating or the like, and a metal (23) such as solder is filled in the hole so as to protrude toward the conductive land (20) on the back surface of the insulating sheet. To protrude. Then, the conductive pattern (16) on the surface of the insulating sheet and the conductive land (20) are electrically connected through the through hole (22), and the electrode pad (19) of the pellet (12) and the conductive land (20) are connected. When the electrical connection is performed by pressurization and thermocompression bonding, the filling metal (23) is also connected, the compression area increases, and the electrical and mechanical connection strength increases. or,
Since the diameter of the through hole can be reduced by an amount corresponding to the increase in the crimping area, the electrode arrangement pitch can be further reduced to increase the number of electrodes and the number of leads.

【0010】更に、図3(a)(b)に示す実施例で
は、絶縁シート(11)の表裏面に形成した導電ランド
(21)と導電パターン(16)とを、内周面に導電層
(24a)を形成した表裏貫通の透孔(24)を介して
電気的接続すると共に、シート裏面上で導電ランド(2
1)を導電パターン(16)との電気的接続部から所定
長、延在し、その延在部(21a)上に金属メッキを施
す。そして、図3(a)に示すように、上記延在部(2
1a)を除いてシート裏面にレジスト膜(25)を被着
形成し、延在部(21a)にペレット(12)の電極パ
ッド(19)を重ねて電気的接続する。そうすると、ペ
レット(12)の電極パッド(19)と導電ランド(2
1)との圧着面積が大きくなって電気的、且つ、機械的
接続強度が増大する。又、上記同様、透孔径を小さく出
来るため、電極配列ピッチを更に小さくして電極数及び
リード本数を増やすことが出来る。
Further, in the embodiment shown in FIGS. 3 (a) and 3 (b), the conductive land (21) and the conductive pattern (16) formed on the front and back surfaces of the insulating sheet (11) are provided with a conductive layer on the inner peripheral surface. (24a) are electrically connected through the front and back through holes (24) formed therein, and the conductive lands (2) are formed on the back surface of the sheet.
1) is extended for a predetermined length from an electrical connection with the conductive pattern (16), and metal plating is applied to the extension (21a). Then, as shown in FIG.
Except for 1a), a resist film (25) is formed on the back surface of the sheet, and an electrode pad (19) of the pellet (12) is superposed on the extending portion (21a) for electrical connection. Then, the electrode pad (19) of the pellet (12) and the conductive land (2)
(1) The crimping area increases, and the electrical and mechanical connection strength increases. Further, similarly to the above, since the diameter of the through hole can be reduced, the electrode arrangement pitch can be further reduced, and the number of electrodes and the number of leads can be increased.

【0011】[0011]

【発明の効果】本発明によれば、絶縁シートの一方の面
に形成した導電パターンと他方の面に形成した導電ラン
ドとを透孔を介して電気的接続し、上記導電ランドにペ
レット電極パッドを重ねて電気的接続したから、電極配
置パターンを任意に設定出来、それに応じてリード本数
を多く、又、そのピッチ間隔を拡げることが可能とな
り、ペレット高密度化に対応出来る。
According to the present invention, the conductive pattern formed on one surface of the insulating sheet and the conductive land formed on the other surface are electrically connected through the through holes, and the conductive land is connected to the pellet electrode pad. Are electrically connected to each other so that the electrode arrangement pattern can be set arbitrarily, the number of leads can be increased accordingly, and the pitch interval can be increased, which can cope with high density of pellets.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)は本発明に係る半導体装置の実施例を示
す部分平面図である。(b)は図1(a)の要部を示す
導電パターンと導電ランド及びペレット電極パッドとの
電気的接続部を示す側断面図である。
FIG. 1A is a partial plan view showing an embodiment of a semiconductor device according to the present invention. FIG. 2B is a side sectional view showing an electrical connection between a conductive pattern showing a main part of FIG. 1A and a conductive land and a pellet electrode pad.

【図2】本発明に係る半導体装置の他の実施例の要部を
示す導電パターンと導電ランド及びペレット電極パッド
との電気的接続部を示す側断面図である。
FIG. 2 is a side sectional view showing an electrical connection between a conductive pattern and a conductive land and a pellet electrode pad showing a main part of another embodiment of the semiconductor device according to the present invention.

【図3】(a)は本発明に係る半導体装置のその他の実
施例の要部を示す導電ランドの部分平面図である。
(b)は図3(a)の要部を示す導電パターンと導電ラ
ンド及びペレット電極パッドとの電気的接続部を示す側
断面図である。
FIG. 3A is a partial plan view of a conductive land showing a main part of another embodiment of the semiconductor device according to the present invention.
FIG. 3B is a side sectional view showing an electrical connection between a conductive pattern showing a main part of FIG. 3A and a conductive land and a pellet electrode pad.

【図4】TAB式半導体装置の一例を示す側断面図であ
る。
FIG. 4 is a side sectional view showing an example of a TAB type semiconductor device.

【図5】TABテープの部分平面図である。FIG. 5 is a partial plan view of the TAB tape.

【符号の説明】[Explanation of symbols]

11 絶縁シート 12 半導体ペレット 13 位置確認孔 16 導電パターン 17 導電ランド 18 透孔 19 電極パッド M 位置マーク DESCRIPTION OF SYMBOLS 11 Insulation sheet 12 Semiconductor pellet 13 Position check hole 16 Conductive pattern 17 Conductive land 18 Through hole 19 Electrode pad M Position mark

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 上面にフラットな電極パッドを多数形成
し、電極パッド形成領域より外方位置に位置確認マーク
を形成した半導体ペレットと、一方の面に導電パターン
を、他の面の上記電極パッドと対応する位置に導電ラン
ドをそれぞれ形成し、他の面の導電ランドとその近傍を
除く部分をエッチングして部分的に肉薄に形成し導電パ
ターン及び導電ランドを透孔を介して電気的接続すると
共に、半導体ペレットの位置確認マークと対応する位置
に位置確認孔を設け、半導体ペレットの電極パッドと導
電ランドが電気的に接続される絶縁シートとを具備した
ことを特徴とする半導体装置。
1. A large number of flat electrode pads are formed on an upper surface.
Position confirmation mark outside the electrode pad formation area
And a conductive pattern on one side
A conductive run on the other surface at a position corresponding to the electrode pad.
And the conductive land on the other surface and its vicinity
Excluded parts are etched to form thin parts and conductive
When the turns and conductive lands are electrically connected through through holes
In both cases, the position corresponding to the position confirmation mark on the semiconductor pellet
Position confirmation holes in the
A semiconductor device comprising: an insulating sheet to which an electric land is electrically connected .
【請求項2】 透孔内に金属を充填して絶縁シート両面
の導電パターンと導電ランドとを電気的接続し、透孔内
に充填した金属を導電ランド側に凸状に突出させたこと
を特徴とする請求項1に記載の半導体装置。
2. A method in which a metal is filled in a through hole to electrically connect a conductive pattern on both surfaces of an insulating sheet and a conductive land, and that the metal filled in the through hole protrudes toward the conductive land. The semiconductor device according to claim 1, wherein:
【請求項3】 絶縁シート面上で導電ランドを導電パタ
ーンとの電気的接続部から所定長、延在し、上記延在部
に半導体ペレットの電極パッドを重ねて電気的接続した
ことを特徴とする請求項1に記載の半導体装置。
3. A conductive land extends on a surface of an insulating sheet from an electrical connection portion with a conductive pattern by a predetermined length, and an electrode pad of a semiconductor pellet is overlapped on the extension portion to be electrically connected. The semiconductor device according to claim 1.
JP03639793A 1993-02-25 1993-02-25 Semiconductor device Expired - Fee Related JP3269506B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03639793A JP3269506B2 (en) 1993-02-25 1993-02-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03639793A JP3269506B2 (en) 1993-02-25 1993-02-25 Semiconductor device

Publications (2)

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JPH06252205A JPH06252205A (en) 1994-09-09
JP3269506B2 true JP3269506B2 (en) 2002-03-25

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Publication number Priority date Publication date Assignee Title
JPH1012661A (en) * 1996-06-19 1998-01-16 Nec Corp Semiconductor device and its manufacture
JP3801300B2 (en) * 1997-03-21 2006-07-26 セイコーエプソン株式会社 Manufacturing method of semiconductor device

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JPH06252205A (en) 1994-09-09

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