JPH03130853A - Bus fault detection system - Google Patents

Abstract

PURPOSE:To point out a faulty processor when a bus interface part of a process has a trouble by confirming the normal operation of each processor via a working bus controller. CONSTITUTION:Each of processors 2 - 5 outputs an existence signal when no bus request is received in a bus selection cycle period and then outputs an existence signal synchronously with a bus request signal when a bus request is received. A bus controller 1 detects the fault of the bus interface part of each of processors 2 - 5 based on a fact whether an existence signal is returned from each processor or not. Thus it is possible to detect the fault of a bus 6 after confirming the normal use of the bus 6 for each processor without deteriorating the availability of the bus 6.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bus failure detection method in a distributed processing system in which a plurality of processors are connected by a bus and the right to use the bus is determined by a bus selection cycle.

(Prior Art) Inter-processor communication in the above-mentioned distributed processing system employs a control method, typified by a polling method, in which each processor is given the right to use the bus through a bus selection cycle when the bus control device is in an open state. It is common to do so.

(Problem to be solved by the invention) Although the conventional bus control method is a simple method as described above,
On the other hand, the measures taken to deal with processor abnormalities were not sufficient. For example, if a failure occurs in the bus interface section, the bus control device may not be able to detect the abnormality at all, and the failure may occur during normal processor communication, so the disadvantage is that it is not possible to determine the location of the failure. was there.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks, and to provide a bus failure detection method that can detect bus failures by confirming that each processor is using the bus normally without reducing bus usage efficiency. It is about providing.

(Means for Solving the Problems) In order to achieve the above object, a bus failure detection method according to the present invention includes a plurality of processors, a bus connecting each of the processors, and a bus selection cycle period when the bus is in an open state. and a bus control device which sets a bus control unit and grants the right to use the bus to one of the processors requesting to use the bus, and during the bus selection cycle period, when each processor has no bus request, outputs a survival signal, and when there is a bus request, outputs the survival signal in synchronization with the bus request signal, and the bus controller controls the bus control of each processor depending on whether or not the survival signal is returned from each processor. It is configured to detect failures in the Innotaface part.

(Example) Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a distributed processing system to which a bus fault detection method according to the present invention is applied.

In this example, four processors are connected.

The bus is controlled by a polling method, in which one pulse of polling is applied to one processor, and each processor uses a counter to request the use of the bus only for polling of its own processor.

Processors 2 to 5 are connected by a bus 6, and communication between the processors is performed through the bus 6. The bus 6 includes a data line 7 through which the data to be transferred passes, a polling line 8 through which the path control bag f11 asks each processor about a path use request, a request line 9 which requests bus use, and a busy line 10 which indicates that the bus is in use. It is controlled by the bus control device 1 and consists of a button and a live signal IIMll indicating that bus access is normally being made to each processor.

FIG. 2 is a time chart of a bus selection cycle in which the bus control device grants the right to use the bus to the processor.

Each signal except data is "1" to indicate validity.

When the processor 2 that was using the bus turns off the busy signal, the bus control device 1 turns on the polling signal to the processor 3, and requests the processor 3 to respond with a request signal if there is a request to use the bus.

Processor 3 does not need to use the bus, so the request signal does not turn off even if the polling signal is turned on, but it turns on the survival signal to indicate that there is no abnormality in its own path interface section and sends a message to the bus control bag fif1 indicating that there is no abnormality. Let me know.

The bus control device 1 confirms that the survival signal of the processor 3 is turned on when the polling signal is turned on, and is turned off at the fall of the polling signal from on to off.

As described above, if the survival signal does not turn on/off in accordance with the polling signal, it is assumed that the processor 3Fi is malfunctioning.

In FIG. 2, a similar check is performed on the processor 4, and the fall of the polling signal indicates that the processor 4 that turned on the request signal has acquired the right to use the bus.

(Effects of the Invention) As explained above, in the bus failure detection method according to the present invention, the bus control device checks whether each processor is operating normally while controlling the bus. This has the effect of pointing out the faulty processor when this occurs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a distributed processing system employing a bus fault detection method according to the present invention. FIG. 2 is a timing chart showing an example of the output of each signal line for a bus selection cycle. 1... Bus control device 2, 3. 4. 5...Processor 6s...Bus T...Data line 8...Polling line 9...Request line 10...Busy line 1 - Survival signal line

Claims (1)

[Claims] a plurality of processors, a bus connecting each of the processors;
In a distributed processing system comprising a bus control device that sets a bus selection cycle period and grants bus use rights to one processor from among processors requesting bus use when the bus is in an open state, , each processor outputs a survival signal when there is no bus request, and outputs a survival signal in synchronization with the bus request signal when there is a bus request, and the bus control device receives the survival signal back from each processor. A bus failure detection method characterized by detecting a failure in a bus interface portion of each processor depending on whether or not there is a failure.