JPH03129831A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03129831A
JPH03129831A JP26968389A JP26968389A JPH03129831A JP H03129831 A JPH03129831 A JP H03129831A JP 26968389 A JP26968389 A JP 26968389A JP 26968389 A JP26968389 A JP 26968389A JP H03129831 A JPH03129831 A JP H03129831A
Authority
JP
Japan
Prior art keywords
film
polyimide resin
metal
resin film
metallic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26968389A
Other languages
Japanese (ja)
Inventor
Takaaki Kobayashi
孝彰 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP26968389A priority Critical patent/JPH03129831A/en
Publication of JPH03129831A publication Critical patent/JPH03129831A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To avoid the surface deterioration and wear of metallic protrusion electrodes by a method wherein the metallic protrusion electrodes are insulation- isolated while the upper surface thereof are being coat-covered with a polyimide resin layer. CONSTITUTION:First and second metallic films 2, 3 as the cathode side current channels are plated, metallic protrusion electrodes 5 comprising metallic plated films thinner than photoresist films 4 are formed on the opening parts of the second metallic films 3; and then a polyimide resin film 6 is formed to flatten the whole surface. Next, the upper layer part of the polyimide resin film 6 is etched away leaving the resin film 6 only on the metallic protrusion electrodes 5; the resist films 4 are peeled off; any unnecessary parts of the first and second metallic films 2, 3 are etched away; and finally the polyimide resin film 6 left on the metallic protrusion electrodes 5 is etched away. That is, the upper parts of the metallic protrusion electrodes 5 are protected by the polyimide resin film 6 when the electrodes 5 are insulation-isolated to be etched away. Through these procedures, the surface deterioration and wear of the metallic protrusion electrodes 6 by etching process can be avoided thereby enabling pressure fixing of the electrodes 5 on a tape carrier to be made highly reliable.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はテープキャリア用の半導体装置の製造方法に利
用され、特に、金属突起電極の製法を改善した半導体装
置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is utilized in a method of manufacturing a semiconductor device for a tape carrier, and particularly relates to a method of manufacturing a semiconductor device that improves the method of manufacturing a metal protrusion electrode.

〔概要〕〔overview〕

本発明は、金属メッキ膜からなる金属突起電極を有する
半導体装置の製造方法において、前記金属突起電極を電
気的に絶縁分離するために不要となった金属膜をエツチ
ング除去する際に、その上層部分をポリイミド樹脂で保
護するようにすることにより、 エツチングによる前記金属突起電極の表面の変質および
減耗を防止し、テープキャリアへの圧着の信頼性の向上
を図ったものである。
The present invention provides a method for manufacturing a semiconductor device having a metal protrusion electrode made of a metal plating film, in which an upper layer portion of the metal film is removed by etching to electrically insulate and separate the metal protrusion electrode. By protecting the metal protruding electrode with polyimide resin, deterioration and wear of the surface of the metal protruding electrode due to etching can be prevented, and the reliability of pressure bonding to the tape carrier can be improved.

〔従来の技術〕[Conventional technology]

従来、この種の金属メッキ膜による金属突起電極を有す
るキャリアテープ用の半導体装置の製造方法は、下地配
線形成終了後に、下地配線と金属メッキ膜との密着力を
強化するための第一の金属膜、およびその上層に下地配
線と金属メッキ膜とが反応することを防止するためのバ
リア膜として第二の金属膜を連続被着して、メッキの際
の電流路を形成し、その後、フォトレジスト膜をマスク
としてメッキを行うことにより、金属メッキ膜よりなる
金属突起電極を形成し、フォトレジスト膜を剥離した後
、前記金属突起電極をマスクとして不要部の第一の金属
膜および第二の金属膜をエツチング除去し、各々の金属
突起電極を絶縁分離していた。
Conventionally, in the manufacturing method of a semiconductor device for a carrier tape having a metal protruding electrode made of this kind of metal plating film, after the formation of the base wiring is completed, a first metal is added to strengthen the adhesion between the base wiring and the metal plating film. A second metal film is continuously deposited on the film and its upper layer as a barrier film to prevent the underlying wiring from reacting with the metal plating film to form a current path during plating. By performing plating using the resist film as a mask, a metal protrusion electrode made of a metal plating film is formed, and after peeling off the photoresist film, unnecessary parts of the first metal film and the second metal film are removed using the metal protrusion electrode as a mask. The metal film was removed by etching, and each metal protrusion electrode was insulated and separated.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

前述した従来のメッキによる金属メッキ膜からなる金属
突起電極形成方法は、メッキ完了後に各々の金属突起電
極を電気的に絶縁分離するために、第一の金属膜および
第二の金属膜を異方性ドライエツチングによりエツチン
グ除去しているので、金属突起電極の表層部もエツチン
グされ、表面層の変質および膜減り等が生じ、テープキ
ャリアの導通面に高信頼のもとて圧着できない欠点があ
る。
In the conventional method for forming metal protruding electrodes made of metal plating films as described above, the first metal film and the second metal film are anisotropically separated in order to electrically insulate and separate each metal protrusion electrode after plating is completed. Since etching is removed by dry etching, the surface layer of the metal protrusion electrode is also etched, resulting in deterioration of the surface layer and thinning of the film, which has the drawback that it cannot be reliably pressed onto the conductive surface of the tape carrier.

本発明の目的は、前記の欠点を除去することにより、表
面層の変質および膜減り等を生ずることなく金属突起電
極を形成でき、テープキャリアの導通面に高信頼にて圧
着できる、半導体装置の製造方法を提供することにある
An object of the present invention is to provide a semiconductor device which can form metal protruding electrodes without causing deterioration of the surface layer or thinning of the film by eliminating the above-mentioned drawbacks, and which can be reliably pressed onto the conductive surface of a tape carrier. The purpose is to provide a manufacturing method.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、素子および下地配線が形成された半導体基板
上に、密着力強化用の第一の金属膜および反応防止用の
第二の金属膜を積層しさらにその上にフォトレジスト膜
を形成しパターンニングし所定位置に開口部を形成する
工程を含む半導体装置の製造方法において、前記第一お
よび第二の金属膜を陰極側の電流路としてメッキを行い
前記第二の金属膜の開口部上に前記フォトレジスト膜の
厚さより薄い膜厚の金属メッキ膜よりなる金属突起電極
を形成する工程店、全面が平坦になるようにポリイミド
樹脂膜を形成する工程と、前記ポリイミド樹脂膜の上層
部をエツチング除去し前記金属突起電極上にのみ前記ポ
リイミド樹脂膜を残す工程と、前記フォトレジスト膜を
剥離除去し、異方性ドライエツチングにより不要部分の
前記第一および第二の金属膜をエツチング除去する工程
と、前記金属突起電極上に残された前記ポリイミド樹脂
膜をエツチング除去する工程とを含むことを特徴とする
In the present invention, a first metal film for reinforcing adhesion and a second metal film for preventing reaction are laminated on a semiconductor substrate on which elements and underlying wiring are formed, and a photoresist film is further formed thereon. In a method for manufacturing a semiconductor device including a step of patterning and forming an opening at a predetermined position, plating is performed using the first and second metal films as current paths on the cathode side, and plating is performed on the opening of the second metal film. A process shop for forming a metal protruding electrode made of a metal plating film thinner than the thickness of the photoresist film, a process for forming a polyimide resin film so that the entire surface is flat, and a process for forming an upper layer of the polyimide resin film. A step of removing the polyimide resin film by etching and leaving the polyimide resin film only on the metal protrusion electrode, and peeling off the photoresist film and removing unnecessary portions of the first and second metal films by anisotropic dry etching. and a step of etching away the polyimide resin film left on the metal protrusion electrode.

〔作用〕[Effect]

本発明においては、金属突起電極の絶縁分離は、前記金
属突起電極上面をポリイミド樹脂層で被覆保護した状態
で行われる。
In the present invention, the insulation separation of the metal protrusion electrode is performed while the upper surface of the metal protrusion electrode is covered and protected with a polyimide resin layer.

従って、エツチングによる前記金属突起電極の表面の変
質および減耗を防止でき、テープキャリアへの圧着の高
信頼性化が可能となる。
Therefore, deterioration and wear of the surface of the metal protrusion electrode due to etching can be prevented, and high reliability of pressure bonding to the tape carrier can be achieved.

〔実施例〕〔Example〕

以下、本発明の実施例について図面を参照して説明する
Embodiments of the present invention will be described below with reference to the drawings.

第1図(a)〜(e)は本発明の第一実施例による半導
体装置の主要製造工程における模式的断面図で、金属突
起電極として金突起電極を形成する場合を示す。
FIGS. 1(a) to 1(e) are schematic cross-sectional views of the main manufacturing steps of a semiconductor device according to a first embodiment of the present invention, showing the case where a gold protrusion electrode is formed as the metal protrusion electrode.

まず、第1図(a)に示すように、素子および下地配線
を完成した後の半導体基板(素子は省略して示しである
)1の表面全体に前記下地配線との密着力を強化するた
めの膜厚的0.5μ0のチタン膜2が被着されており、
さらにその上層には、下地と金突起電極が反応すること
を防止するための膜厚的0.1−の白金膜3が被着され
ている。ここにチタン膜2および白金膜3は基板表面全
体に被着しであるので、メッキを行う際の各全突起電極
間の電流路ともなる。さらにその上層には、メッキを行
う際のマスク材となる膜厚が約25μlの第一のフォト
レジスト膜4が形成されており、金突起電極を形成する
領域に開口部が開口され、白金膜3の一部が露呈してい
る。
First, as shown in FIG. 1(a), in order to strengthen the adhesion with the underlying wiring over the entire surface of the semiconductor substrate 1 (the elements are omitted in the illustration) after completing the elements and underlying wiring. A titanium film 2 with a film thickness of 0.5μ0 is deposited,
Furthermore, a platinum film 3 with a thickness of 0.1-0.1 mm is deposited on the upper layer to prevent reaction between the base and the gold protrusion electrodes. Since the titanium film 2 and the platinum film 3 are adhered to the entire surface of the substrate, they also serve as current paths between all the protruding electrodes during plating. Further, on the upper layer, a first photoresist film 4 with a thickness of about 25 μl is formed to serve as a mask material during plating, and an opening is opened in the area where the gold protrusion electrode is to be formed, and a platinum film is formed. Part 3 is exposed.

その後、第1図(ハ)に示すように、半導体基板1を金
メッキ液中に浸漬し、チタン膜2および白金膜3を電流
路としてメッキ装置側の陽極電極板との間に電流を流し
てメッキを行うことにより、フォトレジスト膜4の開口
部に露呈されている白金膜3上に金メッキ層、すなわち
膜厚が約20pの全突起電極5を形成する。ここに、全
突起電極5は、フォトレジスト膜の膜厚よりも薄く形成
し、開口部に約5μmの低い段が形成されるようにして
おく。
Thereafter, as shown in FIG. 1(C), the semiconductor substrate 1 is immersed in a gold plating solution, and a current is passed between the titanium film 2 and the platinum film 3 as current paths between the anode electrode plate on the plating apparatus side. By performing plating, a gold plating layer, that is, a fully protruding electrode 5 having a film thickness of about 20p is formed on the platinum film 3 exposed in the opening of the photoresist film 4. Here, all the protruding electrodes 5 are formed to be thinner than the photoresist film so that a low step of about 5 μm is formed in the opening.

その後、基板表面全体にポリイミド樹脂膜6を約lOμ
mの厚さに塗布形成し、開口部の凹部にポリイミド樹脂
を充てんし、基板表面を平坦化する。
After that, a polyimide resin film 6 of about 10μ is applied to the entire surface of the substrate.
The polyimide resin is applied to a thickness of m, and the concave portion of the opening is filled with polyimide resin, and the surface of the substrate is flattened.

その後、第1図(C)に示すように、ポリイミド樹脂膜
6を基板表面内で均一にエツチングし、開口部の凹部す
なわち全突起電極5の直上のみにポリイミド樹脂膜6を
残す。
Thereafter, as shown in FIG. 1C, the polyimide resin film 6 is etched uniformly within the substrate surface, leaving the polyimide resin film 6 only in the recesses of the openings, that is, directly above all the protruding electrodes 5.

その後、第1図(d)に示すように、フォトレジスト膜
4を全部除去し、アル2ゴンガスを用いた異方性ドライ
エツチングにより白金膜3およびチタン膜2を連続エツ
チングし、各々の全突起電極5を電気的に絶縁分離する
。このとき、全突起電極5はその上層部がポリイミド樹
脂膜6で保護されているため、エツチングされることは
なくメッキ完了後の状態を保持することができる。
Thereafter, as shown in FIG. 1(d), the photoresist film 4 is completely removed, and the platinum film 3 and titanium film 2 are continuously etched by anisotropic dry etching using argon gas to remove all the protrusions of each. The electrodes 5 are electrically insulated and separated. At this time, since the upper layer of all the protruding electrodes 5 is protected by the polyimide resin film 6, they are not etched and can maintain the state after plating is completed.

その後、第1図(e)に示すように、ポリイミド樹脂膜
6をヒドラジン系の薬液によりエツチング除去すること
により、所望の半導体装置が完成する。
Thereafter, as shown in FIG. 1(e), the polyimide resin film 6 is removed by etching with a hydrazine-based chemical solution, thereby completing a desired semiconductor device.

従って、この方法によると、全突起電極5はその絶縁分
離エツチング時に、ポリイミド樹脂膜6でその上層部が
保護されているため、エツチングにより変質したり膜減
りしたりすることがなく、全突起電極5をテープキャリ
アの導通面に圧着させたときの機械的および電気的接続
を高い信頼性で行うことができる。
Therefore, according to this method, since the upper layer of the all-protruding electrode 5 is protected by the polyimide resin film 6 during the insulation separation etching, the entire protruding electrode 5 is not deteriorated or thinned by etching. When 5 is crimped onto the conductive surface of the tape carrier, mechanical and electrical connections can be made with high reliability.

第2図(a)〜(匂は本発明の第二実施例による半導体
装置の主要工程における模式的断面図である。
FIGS. 2(a) to 2(a) are schematic cross-sectional views of main steps of a semiconductor device according to a second embodiment of the present invention.

ここで、第2図(a)〜(C)は前述の第一実施例と同
様であり、素子を完成した後の半導体基板210表面に
、密着力を強化するための膜厚的0.5μmのチタン膜
22および反応を防止するための膜厚的0.1μIの白
金膜23が形成されており、膜圧的7−のポジ型の第一
のフォトレジスト膜24をマスクとしてメッキを行い、
膜厚的3JIJBの第一の金配線28が形成されており
、その直上にはエッチバックにより残された膜厚的4μ
mの第一のポリイミド樹脂膜26が形成されている。
Here, FIGS. 2(a) to 2(C) are similar to the first embodiment described above, and after the device is completed, a film of 0.5 μm in thickness is applied to the surface of the semiconductor substrate 210 to strengthen adhesion. A titanium film 22 and a platinum film 23 with a film thickness of 0.1 μI for preventing reactions are formed, and plating is performed using a positive type first photoresist film 24 with a film thickness of 7- as a mask.
A first gold wiring 28 with a film thickness of 3JIJB is formed, and directly above it, a film with a film thickness of 4μ left by etching back is formed.
m first polyimide resin films 26 are formed.

次に、第2図(6)のように、全突起電極を形成するた
めのメッキ時のマスクとなる膜厚約20即のポジ型の第
二のきフォトレジスト膜27を第一の7オトレジスト膜
24直上に形成する。ここで、ポリイミド樹脂膜26は
、ポジ型レジストの現像液に溶解してしまうことから、
第二のフォトレジスト膜27をパターン化する際に全突
起電極形成領域内の第一のポリイミド樹脂26は全て除
去され、第一の金配線28が露呈する。
Next, as shown in FIG. 2 (6), a positive second photoresist film 27 with a film thickness of approximately 20 mm, which will serve as a mask during plating to form all protruding electrodes, is applied to the first 70 mm photoresist film. It is formed directly above the membrane 24. Here, since the polyimide resin film 26 is dissolved in the developer of the positive resist,
When patterning the second photoresist film 27, all of the first polyimide resin 26 within the entire projecting electrode formation region is removed, and the first gold wiring 28 is exposed.

その後、第2図(e)に示すように、第一の金配線28
および第一のポリイミド樹脂膜26を形成した際と同様
にして、第一の金配線28上に膜厚的15μmの全突起
電極25を形成し、その直上にエッチバック方式により
膜厚的5μmの第二のポリイミド樹脂膜29を形成する
Thereafter, as shown in FIG. 2(e), the first gold wiring 28
Then, in the same manner as when forming the first polyimide resin film 26, a fully protruding electrode 25 with a film thickness of 15 μm is formed on the first gold wiring 28, and a film thickness of 5 μm with a film thickness of 5 μm is formed directly above it by an etch-back method. A second polyimide resin film 29 is formed.

その後、第2図(f)に示すように、第一実施例と同様
にして、第一のフォトレジスト膜24および第二のフォ
トレジスト膜27を全て剥離した後、異方性ドライエツ
チングで白金膜23およびチタン膜22を同時にエツチ
ング除去する。
Thereafter, as shown in FIG. 2(f), the first photoresist film 24 and the second photoresist film 27 are completely peeled off in the same manner as in the first embodiment, and then platinum is etched by anisotropic dry etching. The film 23 and the titanium film 22 are removed by etching at the same time.

その後、第2図((至)に示すように、第一の金配線2
8上の第一のポリイミド樹脂膜26および全突起電極2
5上の第二のポリイミド樹脂膜29を同時にウェットエ
ツチングで除去することにより、所要の半導体装置が完
成する。
After that, as shown in FIG.
8 and the first polyimide resin film 26 and all protruding electrodes 2
By simultaneously removing the second polyimide resin film 29 on 5 by wet etching, the desired semiconductor device is completed.

ここで、密着力を強化するチタン膜22および反応を防
止する白金膜23は他の金属を使用してもよく、また、
全突起電極には全以外の金属を使用することもできる。
Here, other metals may be used for the titanium film 22 that strengthens adhesion and the platinum film 23 that prevents reaction.
Metals other than all can also be used for the all-protruding electrode.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、各々の金属突起電極を
電気的に絶縁分離するために不要となった金属膜をエツ
チング除去する際に、金属突起電極の上層部をポリイミ
ド樹脂膜ングすることにより、エツチングによりその表
面部が変質したり膜減りしたりすることがな(なるため
、金属突起電極をテープキャリアの導通面に高信頼性の
もとで圧着することができる効果がある。
As explained above, the present invention involves coating the upper layer of the metal protrusion electrodes with a polyimide resin film when removing unnecessary metal films for electrically insulating and separating each metal protrusion electrode. As a result, the surface portion is not altered in quality or the film is thinned due to etching (this has the effect that the metal protrusion electrode can be pressure-bonded to the conductive surface of the tape carrier with high reliability).

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(e)は本発明の第一実施例による半導
体装置の主要製造工程における模式的断面図。 第2図(a)〜(樋は本発明の第二実施例による半導体
装置の主要製造工程における模式的断面図。 1.21・・・半導体基板、2.22・・・チタン膜、
3.23・・・白金膜、4.24.27・・・フォトレ
ジスト膜、5.25・・・全突起電極、6.26.29
・・・ポリイミド樹脂膜、28・・・金配線。
FIGS. 1(a) to 1(e) are schematic sectional views showing main manufacturing steps of a semiconductor device according to a first embodiment of the present invention. FIGS. 2(a) to 2(a) are schematic cross-sectional views of the main manufacturing steps of a semiconductor device according to the second embodiment of the present invention. 1.21: Semiconductor substrate, 2.22: Titanium film,
3.23...Platinum film, 4.24.27...Photoresist film, 5.25...All protruding electrodes, 6.26.29
...Polyimide resin film, 28-gold wiring.

Claims (1)

【特許請求の範囲】 1、素子および下地配線が形成された半導体基板上に、
密着力強化用の第一の金属膜および反応防止用の第二の
金属膜を積層しさらにその上にフォトレジスト膜を形成
しパターンニングし所定位置に開口部を形成する工程を 含む半導体装置の製造方法において、 前記第一および第二の金属膜を陰極側の電流路としてメ
ッキを行い前記第二の金属膜の開口部上に前記フォトレ
ジスト膜の厚さより薄い膜厚の金属メッキ膜よりなる金
属突起電極を形成する工程と、 全面が平坦になるようにポリイミド樹脂膜を形成する工
程と、 前記ポリイミド樹脂膜の上層部をエッチング除去し前記
金属突起電極上にのみ前記ポリイミド樹脂膜を残す工程
と、 前記フォトレジスト膜を剥離除去し、異方性ドライエッ
チングにより不要部分の前記第一および第二の金属膜を
エッチング除去する工程と、前記金属突起電極上に残さ
れた前記ポリイミド樹脂膜をエッチング除去する工程と を含むことを特徴とする半導体装置の製造方法。
[Claims] 1. On a semiconductor substrate on which elements and underlying wiring are formed,
A method for manufacturing a semiconductor device including the step of laminating a first metal film for strengthening adhesion and a second metal film for preventing reaction, and further forming a photoresist film thereon and patterning it to form an opening at a predetermined position. In the manufacturing method, plating is performed using the first and second metal films as current paths on the cathode side, and a metal plating film having a thickness thinner than the thickness of the photoresist film is formed on the opening of the second metal film. a step of forming a metal protrusion electrode; a step of forming a polyimide resin film so that the entire surface is flat; and a step of etching away the upper layer of the polyimide resin film to leave the polyimide resin film only on the metal protrusion electrode. and removing the photoresist film and etching away unnecessary portions of the first and second metal films by anisotropic dry etching, and removing the polyimide resin film left on the metal protrusion electrodes. A method for manufacturing a semiconductor device, comprising the step of removing by etching.
JP26968389A 1989-10-16 1989-10-16 Manufacture of semiconductor device Pending JPH03129831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26968389A JPH03129831A (en) 1989-10-16 1989-10-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26968389A JPH03129831A (en) 1989-10-16 1989-10-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03129831A true JPH03129831A (en) 1991-06-03

Family

ID=17475740

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26968389A Pending JPH03129831A (en) 1989-10-16 1989-10-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03129831A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007134458A (en) * 2005-11-09 2007-05-31 Shinko Electric Ind Co Ltd Manufacturing method of wiring board and manufacturing method of semiconductor device
JP2009185589A (en) * 2008-02-08 2009-08-20 Shinko Kogyo Co Ltd Vacuum external wall panel used also as inspection window for device with inside-outside temperature difference
JP2011054652A (en) * 2009-08-31 2011-03-17 Toppan Printing Co Ltd Semiconductor device and method of manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007134458A (en) * 2005-11-09 2007-05-31 Shinko Electric Ind Co Ltd Manufacturing method of wiring board and manufacturing method of semiconductor device
JP4718305B2 (en) * 2005-11-09 2011-07-06 新光電気工業株式会社 Wiring substrate manufacturing method and semiconductor device manufacturing method
JP2009185589A (en) * 2008-02-08 2009-08-20 Shinko Kogyo Co Ltd Vacuum external wall panel used also as inspection window for device with inside-outside temperature difference
JP2011054652A (en) * 2009-08-31 2011-03-17 Toppan Printing Co Ltd Semiconductor device and method of manufacturing the same

Similar Documents

Publication Publication Date Title
JP2809088B2 (en) Protruding electrode structure of semiconductor device and method for forming the protruding electrode
US4141782A (en) Bump circuits on tape utilizing chemical milling
JPH03129831A (en) Manufacture of semiconductor device
JPH02253628A (en) Manufacture of semiconductor device
JPH02277242A (en) Manufacture of semiconductor device
JPH03198342A (en) Manufacture of semiconductor device
JP2751242B2 (en) Method for manufacturing semiconductor device
JPH0437033A (en) Forming method of bump electrode
JPS62160744A (en) Manufacture of semiconductor device
JP2748530B2 (en) Method for manufacturing semiconductor device
JPS63122248A (en) Manufacture of semiconductor device
JPS6336548A (en) Semiconductor device and manufacture thereof
JP2874184B2 (en) Method for manufacturing semiconductor device
JP2985426B2 (en) Semiconductor device and manufacturing method thereof
JPS62281356A (en) Manufacture of semiconductor device
JP3119352B2 (en) Method for forming plated structure of semiconductor device
JPH07221108A (en) Structure of electrode of semiconductor device and formation of electrode
JPH02139934A (en) Manufacture of integrated circuit
JPH10340907A (en) Formation of protruding electrode
JPH0350734A (en) Manufacture of integrated circuit
JPH04307737A (en) Manufacture of semiconductor device
JP2621186B2 (en) Method of forming transfer bump
JP3049872B2 (en) Method for manufacturing semiconductor device
JPS628030B2 (en)
JPH04279031A (en) Manufacture of semiconductor device