JPH0312816B2 - - Google Patents

Info

Publication number
JPH0312816B2
JPH0312816B2 JP58126967A JP12696783A JPH0312816B2 JP H0312816 B2 JPH0312816 B2 JP H0312816B2 JP 58126967 A JP58126967 A JP 58126967A JP 12696783 A JP12696783 A JP 12696783A JP H0312816 B2 JPH0312816 B2 JP H0312816B2
Authority
JP
Japan
Prior art keywords
frequency
highway
station
bypass
local
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58126967A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6019339A (ja
Inventor
Hideo Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP12696783A priority Critical patent/JPS6019339A/ja
Publication of JPS6019339A publication Critical patent/JPS6019339A/ja
Publication of JPH0312816B2 publication Critical patent/JPH0312816B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H04L12/422—Synchronisation for ring networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)
JP12696783A 1983-07-14 1983-07-14 デ−タハイウエイの制御方法 Granted JPS6019339A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12696783A JPS6019339A (ja) 1983-07-14 1983-07-14 デ−タハイウエイの制御方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12696783A JPS6019339A (ja) 1983-07-14 1983-07-14 デ−タハイウエイの制御方法

Publications (2)

Publication Number Publication Date
JPS6019339A JPS6019339A (ja) 1985-01-31
JPH0312816B2 true JPH0312816B2 (cs) 1991-02-21

Family

ID=14948325

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12696783A Granted JPS6019339A (ja) 1983-07-14 1983-07-14 デ−タハイウエイの制御方法

Country Status (1)

Country Link
JP (1) JPS6019339A (cs)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0831869B2 (ja) * 1987-02-23 1996-03-27 株式会社日立製作所 データ伝送方法及びデータ伝送装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5444803A (en) * 1977-09-16 1979-04-09 Hitachi Ltd Synchronization system of loop circuit

Also Published As

Publication number Publication date
JPS6019339A (ja) 1985-01-31

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