JPH03127145A - Information processor - Google Patents

Abstract

PURPOSE:To diagnose the quality of a storage element at a high speed by providing an element control circuit for making element selecting terminals of plural storage elements active only when a write strobe signal arrives in accordance with a control signal, between an element selecting circuit and plural storage elements. CONSTITUTION:Between an output terminal of an element selecting circuit 412 and element selecting inputs of storage elements 413 - 415, an element control circuit 118 is connected. The element control circuit 118 inputs outputs 409 - 411 from the element selecting circuit 412, and signals of a write strobe line 417 and a control line 122, and outputs outputs 119 - 121 corresponding to element selecting input terminals of the storage elements 413 - 415, respectively. In such a state, unless there is an input of a control signal, control is executed so that one of plural storage elements is selected in accordance with an output from the output terminal of the element selecting circuit, and while there is an input of the control signal, when a write strobe signal is inputted, all the element selecting terminal become active so that data can be written in all the storage elements. In such a way, the quality of the storage element can be diagnosed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to an information processing device having a plurality of storage elements.

[Prior Art] Writing data to a storage element in this type of information processing device will be described with reference to FIGS. 4 and 5.

In FIG. 4, memory elements 413, 414, and 415 each have an address selection input terminal group 401 (AO to A11) for specifying a data storage address. Each input terminal of the address selection input terminal group 401 is connected to each address line of an address bus 407 composed of 12 signal lines.

The same applies to the memory elements 414 and 415.

The memory elements 413 to 415 are also. It has a data input/output terminal group 402 (DO to D7) that serves as an output terminal for read data and an input terminal for write data. Each terminal of the data input/output terminal group 402 is connected to each data line of a data bus 406 consisting of eight signal lines. Memory element 41
3 to 415 are read strobe input terminals 40, respectively.
3 write strobe input terminal 404. It has an element selection input terminal 405. The read strobe input terminal 403 is
It is connected to the read strobe line 416. Write strobe input terminal 404 is connected to write strobe line 417.

Element selection circuit 412 activates one of selection outputs 409-411 based on the address from address bus 408. The selection outputs 409 to 411 are the element selection input terminals 40 of the storage elements 413, 414, and 415, respectively.
5 is connected.

The address bus 408 is for selecting one of the plurality of storage elements and consists of four address lines, and is an upper address line of the address bus 407.

In FIG. 4, since the address bus 408 consists of four signal lines, 16 different selection outputs (SO to 515) are possible, but for the sake of simplicity, only three (SO, S
L, 515) is entered. Similarly, the memory element is also 1
There are 6 items, but only 3 are entered.

FIG. 5 is a timing chart for explaining the operation of the device shown in FIG. 4, in which address buses 408, 407 . The contents of data bus 406 are shown respectively.

The selection outputs So, Sl, and S15 are the selection output signals 4 in FIG.
The contents of 09, 410, and 411 are shown respectively.

Data is written to the memory elements 413, 414, and 415 as follows. The address bus 408 in FIG. 5 is the upper address line of the address bus 407 and consists of four address lines, and the combinations 0h-Fh ("h" means 16 lines display, the same applies hereinafter) are possible. First, when the address bus 408 is all O (as shown by section A in FIG. 5)
Only the 1 selection output 409 is at rL (low) level.

All other selection outputs including selection output 410.411 are rH
(High)” level. Since the element selection input 405 of memory element 413 among memory elements 413 to 415 is active at the rLJ level, only memory element 413 is selected and responds to address bus 407 and data bus 406. That is, the address bus 407 is 000h-FFF.
When specified as h, one address in the storage element 413 is selected.

Next, the write strobe line 417 transitions from the rLJ level to the rHJ level within the period when the address bus is established. Memory elements 413 to 415 have element selection input 405 at rLJ level and write strobe line 417 at r
At a transition point 501 from LJ to rHJ, the contents of data bus 406 are written to the address specified by address bus 407. In order to write data to all addresses of the memory element 413, the addresses are sequentially changed from 0OOh to FFFh, and rLJ is applied to the write strobe line 417 for each address.
This is done by causing a transition of rHJ from .

To write to storage element 414, address bus 4
Let 08 be 1h. When the address bus 408 becomes 1h, the element selection circuit 412 selects output 4 as shown in section B.
Only 10 is set as rLJ level and 1 selection output 409.411
All other selection outputs, including , are at rHJ level. As a result, only the memory element 414 is connected to the address bus 4o7° data bus 406. Write strobe line 417
It becomes possible to respond to Similarly, address bus 4
When 08 becomes Fh, only the element selection output 411 becomes rLJ.
All other selection outputs including level and element selection outputs 409 and 410 are at rHJ level.

Therefore, only the memory element 415 is connected to the address bus 4.7, the data bus 406. Write strobe line 417 becomes responsive and the contents of data bus 406 are written into storage element 415 at the transition point of write strobe line 417 from rLJ to rHJ.

[Problems to be Solved by the Invention] In the information processing device according to the prior art, the memory elements 413 to 4
Even if I try to write common data to 15.

address bus 408. By address bus 407.

This process had to be performed for each address, and a large amount of time was required, especially for initializing data in the memory element and diagnosing the quality of the memory element.

The present invention relates to initialization of memory elements using the same data in an information processing apparatus using a large number of memory elements.

An object of the present invention is to provide an information processing device that can quickly diagnose the quality of a storage element and can be operated in a short time after power is turned on.

[Means for Solving the Problems] According to the present invention, a plurality of memory elements receiving a write strobe signal through a common signal line, and a plurality of memory elements connected to each of the element selection terminals provided on the plurality of memory elements, are provided. An information processing device including an element selection circuit having an output terminal and outputting a signal for selecting one of the plurality of storage elements from one of the output terminals in response to an address input,
The device is characterized in that an element control circuit is provided between the element selection circuit and the plurality of storage elements, which activates the element selection terminal of the plurality of storage elements in response to a control signal only when the write strobe signal arrives. An information processing device is obtained.

Regarding an example of the element control circuit.

The device includes a plurality of sets of logic circuits connected to one of the output terminals and receiving the write strobe signal and the control signal, and the logic circuit includes an OR circuit receiving the write strobe signal and the control signal as input. , an AND circuit whose inputs are one output of the output terminal and the output of the OR circuit.

[Function] The element control circuit according to the present invention controls to select one of the plurality of storage elements according to the output from the output terminal of the element selection circuit if no control signal is input. For a certain period of time, when a write strobe signal is input, all element selection terminals are activated to enable data writing to all memory elements.

[Example] An example of the present invention will be described with reference to FIGS. 1, 2, and 3. FIG. 1 is a circuit diagram of an information processing apparatus according to an embodiment of the present invention.

In FIG. 1, the same parts as in FIG. 4 are given the same numbers, and their explanation will be omitted. In this example.

Output terminal of element selection circuit 412 and memory elements 413 to 41
An element limiting circuit 118 is connected between the element selection input of No. 5 and the element selection input of No. 5. The element selection input terminals 405 of the storage elements 413 to 415 are connected to the outputs 119 to 119 of the element control circuit 118, respectively.
121. In this figure as well, only three of the 16 memory elements are shown to simplify the explanation.

Outputs 409 to 411 of the element selection circuit 412 are decoded outputs of the address bus 408. When the four address lines of the address bus are Oh, the decoded output 409 is "L", and otherwise is rHJ. When the address is Fh, the decode output 411 is "L", and otherwise it is rHJ. The element control circuit 118 receives outputs 409 to 411 from the element selection circuit 412.
．． Write strobe line 417. The signal on the control line 122 is input, and outputs 119 to 121 corresponding to the element selection input terminals of the storage elements 413 to 415 are outputted. 12
2 is rLJ when writing to all memory elements simultaneously
This is the control line specified as .

FIG. 2 is a timing chart according to an embodiment of the present invention. FIG. 3 shows an internal circuit for one output of the element control circuit 118. Input 301 is element selection circuit 412
and one input of the AND circuit 305. Input 302 is write strobe line 417
connected to.

It is connected to one input of the OR circuit 306.

Input 303 is connected to control line 122 and OR circuit 306
connected to the other input of the Output 304 is the output of AND circuit 305 and one output of element control circuit 118. An output 307 is the output of the OR circuit 306 and is connected to the other input of the AND circuit 305.

In the following one embodiment of the present invention, the memory elements 413 to 415
The process of writing data will be explained. When the contents of address bus 408 are oh.

Only the output 409 of the element selection circuit 412 is rLJ and output 4
All other outputs including 10 and 411 are rl (J. Next, when the control line 122 is rLJ, the element control circuit 1
Outputs 119 to 121 of 18 are from FIG. 3. When the write strobe input 302 becomes rLJ, the output 307 of the OR circuit 306 becomes rLJ, and the output 304 (that is, including the element control outputs 119 to 120) is synchronized with the write strobe signal. Then, it becomes rLJ. In other words, the control line 122 is r
In the case of LJ, regardless of the contents of address bus 408,
The selection input terminal of each storage element becomes rLJ in synchronization with the write strobe signal. Each memory element 413 to 415 has an element selection input terminal rLJ and a write strobe input terminal r
At each transition point from LJ to rHJ (see numeral 201 in FIG. 2), the contents of the data bus 406 are transferred to the address bus 40.
Write to the address shown in 7. Therefore, while switching the address bus 407 from 000h to FFFh.

If writing is performed, all of the storage elements 413-415 will be written at once. Also, the control line 122 is r
In the case of HJ, the output 307 of the OR circuit 306 in FIG.
This is because the signal becomes "H" and only one element control output 119-121 corresponding to one of the element selection outputs 409-411 is output.

Storage elements 413-415 are never written to at the same time.

[Effects of the Invention] As explained above, in one embodiment of the present invention, data can be written to a plurality of memory elements in the time required for one memory element, and as the number of memory elements increases,
The effects of the present invention will become more noticeable. For this reason, memory element quality diagnosis is performed in information processing devices that use a large number of memory elements.

Alternatively, according to the present invention, the initialization operation by writing the same data can be performed extremely quickly.

This has the effect of providing an information processing device capable of high-speed response and high-speed processing.

[Brief explanation of the drawing]

Figure S1 is a circuit diagram of an embodiment of the present invention, Figure 2 is a timing chart diagram for explaining the operation of an embodiment of the present invention, Figure 3 is a circuit diagram of an element control circuit of an embodiment of the present invention, and Figure 3 is a circuit diagram of an element control circuit of an embodiment of the present invention. FIG. 4 is a circuit diagram of a conventional information processing device, and FIG. 5 is a timing chart for explaining the operation of the conventional device. 401... Address input terminal, 402... Data input/output terminal group, 403... Read strobe input terminal, 404... Write strobe input terminal, 405...
...Element selection input terminal, 406...Data bus, 40
7...Address bus, 408...Address bus, 4
09-411...Element selection output, 412...Element selection circuit, 413-415...Storage element, 416...
Read strobe line, 417...Write strobe line. 118... Element control circuit, 119-121... Element control output. 2...Control line. 401st near address input terminal 402: data input/output terminal 403: m output strobe input resistor 409411: element selection output 412: element selection circuit 413.415: storage element 406: data path 407.408 near address bus 118; element Control 31 circuit 122: Control line Fig. 2 01 Transition point Fig. 3 03 Fig. 4 06

Claims (1)

[Claims] 1) Address input device having a plurality of memory elements that receive a write strobe signal through a common signal line and a plurality of output terminals connected to each of the element selection terminals provided on the plurality of memory elements. an information processing device that includes an element selection circuit that outputs a signal from one of the output terminals to select one of the plurality of storage elements in accordance with the element selection circuit and the plurality of storage elements; An information processing device comprising: an element control circuit that activates element selection terminals of the plurality of storage elements only when the write strobe signal arrives in response to a control signal. 2) The information processing device according to claim 1, wherein the element control circuit includes a plurality of sets of logic circuits connected to one of the output terminals and receiving the write strobe signal and the control signal. Information processing device. 3) The information processing device according to claim 2, wherein the logic circuit has an OR circuit which receives the write strobe signal and the control signal as input, and an output of one of the output terminals and an output of the OR circuit. An information processing device comprising an AND circuit.