JPH03126258A - Optoelectronic integrated circuit for reception - Google Patents
Optoelectronic integrated circuit for receptionInfo
- Publication number
- JPH03126258A JPH03126258A JP26703289A JP26703289A JPH03126258A JP H03126258 A JPH03126258 A JP H03126258A JP 26703289 A JP26703289 A JP 26703289A JP 26703289 A JP26703289 A JP 26703289A JP H03126258 A JPH03126258 A JP H03126258A
- Authority
- JP
- Japan
- Prior art keywords
- fet
- gate
- resist
- integrated circuit
- lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005693 optoelectronics Effects 0.000 title claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 230000005669 field effect Effects 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 8
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 4
- 239000013078 crystal Substances 0.000 abstract description 3
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 101150079361 fet5 gene Proteins 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- OKKJLVBELUTLKV-UHFFFAOYSA-N methanol Substances OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は受信用の光電子集積回路(以下QEICと略称
する)に関し、特にInGaAs−PINフォトダイオ
ード等の受光用素子とGaAs 電界効果トランジス
タ(以下FET)を集積した0IICに関するものであ
る。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a receiving optoelectronic integrated circuit (hereinafter abbreviated as QEIC), and in particular to a light receiving element such as an InGaAs-PIN photodiode and a GaAs field effect transistor (hereinafter abbreviated as QEIC). This relates to an 0IIC that integrates FETs.
第2図(a)は、例えば下記文献に示された従来の1H
G4As 7オトダイオードとGaAa FETを集積
した受信用0BICを示す上面図であり、第2回出)は
、第2図(alのA−A’及びB−B’断面を模式的に
組み合わせて示したものである。図において、1はGa
ps基板、2はGaAB−F BTのゲート電極、3は
ソース電極、4はドレイン電極、5はFgT部である。FIG. 2(a) shows, for example, the conventional 1H shown in the following document.
It is a top view showing a receiving 0BIC that integrates G4As 7 Otodiodes and GaAa FETs, and the second publication) is a top view showing a schematic combination of the A-A' and B-B' cross sections of al. In the figure, 1 is Ga
PS substrate, 2 is a gate electrode of GaAB-FBT, 3 is a source electrode, 4 is a drain electrode, and 5 is an FgT section.
また、6はInGaAs−PD(フォトダイオード)部
、7はn型領域、8はバッファ層、9はn型1nGaA
6受光層、101’tn型InP窓層、11はp型数散
仙域、12はPD6のpm極である。Further, 6 is an InGaAs-PD (photodiode) part, 7 is an n-type region, 8 is a buffer layer, and 9 is an n-type 1nGaA
6 is a light-receiving layer, 101'tn type InP window layer, 11 is a p-type scattering region, and 12 is a pm pole of PD6.
ここで、n型InGaA3受光層9内のpn接合の空乏
層9内のpn接合の空乏層で吸収された光は、電子ホー
ル対を発生し、これにより発生した電流が信号として外
部抵抗に流れ、その電位が信号としてゲート電極2に印
加されFET部5部幅1幅るようになされている。Here, the light absorbed in the pn junction depletion layer in the pn junction depletion layer 9 in the n-type InGaA3 light-receiving layer 9 generates electron-hole pairs, and the generated current flows as a signal to the external resistance. The potential is applied as a signal to the gate electrode 2 to increase the width of the FET section 5 by one width.
この従来の0EICの構成においては、GaAs基板1
上に、転位密度を下げるためのバッファ層8を介在し、
InGaAs 、InP等のInP系材料をMOCVD
法等によシ順次結晶成長した後、20部6を島状に残し
て、これらInP系材料を除去し、GaAs基板1を露
出させた後、この部分にFET5をつくる。In this conventional 0EIC configuration, the GaAs substrate 1
A buffer layer 8 is interposed thereon to lower the dislocation density,
MOCVD of InP-based materials such as InGaAs and InP
After sequential crystal growth by a method such as a method, the InP-based material is removed leaving 20 parts 6 in the form of islands, and after exposing the GaAs substrate 1, the FET 5 is formed in this part.
このとき、上記FIST 5のゲート電極2の長手方向
(ゲート幅方向)は一般に、基板として(100)基板
を用いた場合、〔011〕方向にとられる場合が多い。At this time, the longitudinal direction (gate width direction) of the gate electrode 2 of the FIST 5 is generally set in the [011] direction when a (100) substrate is used as the substrate.
また、島状の20部6の形状は〔011)、[011〕
方向の各2組の線で囲まれた矩形とするのが、0F2I
Cのチップ面積有効利用の見地からは有利であシ、従来
の0EICではその様になっていた。なお、上記文献と
しては、IEEEトランザクションオンエレクトロンデ
バイス(Transnaction on Elect
ron Devices)。In addition, the shape of the island-like 20 parts 6 is [011], [011]
The rectangle surrounded by two sets of lines in each direction is 0F2I.
This is advantageous from the standpoint of effective use of the C chip area, and was the case with conventional 0EICs. The above document includes IEEE Transaction on Electron Device (Transaction on Electron Device).
Ron Devices).
VOL、35 、属8.1284(1988)がある。VOL, 35, Gen. 8.1284 (1988).
従来の受信用0EICは以上の様に構成されていること
、及び20部6とFET部5の段差が5〜10μmと大
きいことから、Flil:Tの製作プロセスにおいて、
ソースおよびドレイン電極3,4やゲート電極2の写真
製版工程のレジスト塗布工程において20部6の周辺で
レジスト溜υ等が発生し、レジストの厚い佃域や薄い領
域ができる、いわゆる塗布むらが生じやすい。従って、
1μm以下の微細パターンをPD部の近くに形成するこ
とが困難であυ、OE工Cの高速化、高利得化等の高性
能化が困難であるという問題点があった。Since the conventional receiving 0EIC is configured as described above and the difference in level between the 20 part 6 and the FET part 5 is as large as 5 to 10 μm, in the manufacturing process of Flil:T,
In the resist coating process of the photolithography process for the source and drain electrodes 3 and 4 and the gate electrode 2, resist accumulation υ occurs around the 20 part 6, resulting in so-called coating unevenness, where thick resist areas and thin resist areas are created. Cheap. Therefore,
There is a problem in that it is difficult to form a fine pattern of 1 μm or less near the PD section, and it is difficult to improve performance such as increasing the speed and gain of the OE process.
また、20部6の周辺の段差のエツチングに際し、FE
T5のゲート方向と、ゲートに垂直な方向で一方の段差
は順メサとなるが、一方は逆メサが生じ、レジストのカ
バーリング性が悪くなるため、ゲート電極形成のための
リフトオフ時に、不必要な電極がこの部分に残る等の問
題点もあった。Also, when etching the steps around the 20 part 6, FE
One step between the gate direction of T5 and the direction perpendicular to the gate becomes a forward mesa, but the other step becomes a reverse mesa, which deteriorates the coverage of the resist. There were also problems such as the electrode remaining in this area.
本発明は上記のような問題点を解消するためになされた
ものであ、Q、PD部の段差があっても、FETを形成
すべき部分のレジスト厚を薄く、均一に形成でき、これ
によシPD部とFET部の距離を短かくしても高性能の
FITが得られる受信用ogrcを得ることを目的とす
る。The present invention has been made to solve the above-mentioned problems, and even if there is a step difference in the Q, PD section, the resist thickness in the part where the FET is to be formed can be formed thin and uniformly, and this can be achieved by It is an object of the present invention to obtain a receiving OGRC that can obtain a high-performance FIT even if the distance between the PD section and the FET section is shortened.
本発明に係る受信用0EICは、島状のPD部の周辺部
を、FIETのゲート方向に対し各々±45゜またはこ
れに近い角度をなすような2組の線で囲まれた矩形とな
るように形成したものである。The receiving 0EIC according to the present invention has a rectangular shape in which the periphery of the island-shaped PD section is surrounded by two sets of lines each forming an angle of ±45° or close to this with respect to the FIET gate direction. It was formed in
本発明においては、FETのゲートの長手方向に対し±
45°に近い角度をなす線で囲まれた矩形の島状のPD
部は、フォトレジストを塗布スる際、レジストが広がる
障壁となりに<<、レジスト溜シが生じにくいため、F
gTを形成すべき部分のレジストの厚さを均一に薄くす
ることができる。In the present invention, ±
A rectangular island PD surrounded by lines forming an angle close to 45°
F
The thickness of the resist in the portion where gT is to be formed can be made uniformly thin.
以下、本発明の実施例を図について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第1図(a)は本発明の一実施例による受信用ogIC
を示す上面図である。第1図(a)において、1は半絶
縁性のGaAs基板、2はGaAs* FETのゲート
電極、3はソース電極、4はドレイン電極、5はFET
部、6は島状のInGaAs −PD部である。ここで
、島状PD部6は、FET5 のゲート電極2の長手
方向、すなわちゲート幅方向に対し、図示する如く±4
5°またはこれに近い角度をなす線で囲まれた矩形を有
している。このとき、(100)GaAs基板1を用い
て、この種の0FICを作製する場合、GaAs−FE
T 5 のゲート幅方向は〔011〕 にとるのが−
船釣である。従って、この実施例の20部6は、これに
対し45°の角度をなす、〔001〕 または〔011
〕 方向の2組の線で取り囲む島状となるように、Ga
ps基板1上のIHP 、InGaAs等のPD用結晶
を、所定の写真製版、エツチング技術によシ除去するこ
とによシ形成されている。なお図中、同一符号は同一ま
たは相当部分を示している。FIG. 1(a) shows a receiving og IC according to an embodiment of the present invention.
FIG. In FIG. 1(a), 1 is a semi-insulating GaAs substrate, 2 is a gate electrode of a GaAs*FET, 3 is a source electrode, 4 is a drain electrode, and 5 is a FET.
Sections and 6 are island-shaped InGaAs-PD sections. Here, the island-like PD portion 6 is ±4 as shown in the figure with respect to the longitudinal direction of the gate electrode 2 of the FET 5, that is, the gate width direction.
It has a rectangle surrounded by lines forming an angle of 5° or close to this. At this time, when producing this type of 0FIC using the (100) GaAs substrate 1, GaAs-FE
The gate width direction of T 5 is set to [011] -
Boat fishing. Therefore, the 20 part 6 of this example makes an angle of 45° with respect to [001] or [011
] Ga is formed into an island shape surrounded by two sets of lines in the direction
It is formed by removing PD crystals such as IHP, InGaAs, etc. on the PS substrate 1 using predetermined photolithography and etching techniques. In the drawings, the same reference numerals indicate the same or corresponding parts.
この実施例による受信用0EICにおいては、FET5
のゲート電極2やソース−ドレイン電極3.4の形成工
程でレジストを塗布する際、第2図(c)に示すような
従来の0ErCで見られたレジストの流れ(矢印の方向
)21が20部6の段差にブロックされることもなく、
第1図(b)のように、スムースなレジストの流れ21
が得られ、PD部6によシ近いところまで、薄い例えば
1μm程度のレジスト膜を均一に塗布することができる
。In the receiving 0EIC according to this embodiment, FET5
When applying resist in the process of forming the gate electrode 2 and source-drain electrodes 3.4, the resist flow (direction of the arrow) 21 observed in the conventional 0ErC as shown in FIG. It is not blocked by the step in section 6,
Smooth resist flow 21 as shown in Figure 1(b)
is obtained, and a thin resist film of, for example, about 1 μm can be uniformly applied to a portion close to the PD section 6.
従って、GaAs m FETの高速化、高利得化のた
めには、ゲート長をできるだけ小さくシ、例えば1μm
以下の微細パターン化が必要となるが、本発明を用いる
ことによ、り、PD部60段差が5μm程度あっても、
PDから50μm程度の近い距離に1μm程度のゲート
長の微細パターンが十分形成可能となる。Therefore, in order to increase the speed and gain of GaAs mFET, the gate length must be made as small as possible, for example, 1 μm.
Although the following fine patterning is required, by using the present invention, even if the PD section 60 has a step difference of about 5 μm,
A fine pattern with a gate length of about 1 μm can be sufficiently formed at a short distance of about 50 μm from the PD.
また、PD部6の周辺は(001)または[:011]
面となっており、これらの面は、異方性のおるInP系
材料のエツチング液、例えばBr−メタノール液等でエ
ツチングした場合でも、逆メサを形成することがなく、
基板にほぼ垂直な段差を形成することができる。従って
、PD部6周辺のレジストのカバリングも逆メサがある
場合と比べ良好であシ、リフトオフ法によりゲート電極
を形成する際、電極金属の残渣が発生するという、従来
の逆メサの段差を有する0EICの問題点も解消される
。Also, the area around the PD section 6 is (001) or [:011]
These surfaces do not form an inverted mesa even when etched with an anisotropic InP-based material etching solution, such as a Br-methanol solution.
It is possible to form a step substantially perpendicular to the substrate. Therefore, the covering of the resist around the PD section 6 is better than when there is a reverse mesa, and when forming a gate electrode by the lift-off method, electrode metal residue is generated, which is a step difference in the conventional reverse mesa. The problem of 0EIC is also solved.
なおこの実施例では、GaAs基板上にGaAs−FE
Tと InGaAs @PDを集積した受信用0EIC
の例について示したが、Si基板上に InGaAs
mPD と Si@MO8FETを集積した。grcや
、InP基板上にGaAs llFETとInGaAS
lIPD を集積した。grcについても適用できるこ
とは言うまでもない。In this example, GaAs-FE is formed on the GaAs substrate.
0EIC for reception integrated with T and InGaAs @PD
In the example shown above, InGaAs on a Si substrate
mPD and Si@MO8FET were integrated. GaAs llFET and InGaAS on grc or InP substrate
IPD was accumulated. Needless to say, this can also be applied to grc.
以上のように本発明によれば、段差のあるPD部を、F
F、Tのゲートの長手方向に対し、±45゜に近い角度
をなす線で囲まれた矩形となるように島状に形成したの
で、レジスト塗布工程において、FETを形成すべき領
域のレジスト膜厚を薄く、しかも均一に塗布することが
可能となり、狭いゲート電極のFgTを得ることができ
る。これにより、高速、高利得の受信DEICを高い歩
留9で製作するととができる。また、PDの周辺段差部
は逆メサが形成されないため、レジストのカバリングが
良くなシ、電極の残漬によるPD部のショート等の特性
不良が減少し、0EICの歩留りが向上するという付随
的な効果もある。As described above, according to the present invention, the PD section with a step can be
Since the island shape was formed into a rectangular shape surrounded by lines forming an angle of approximately ±45° with respect to the longitudinal direction of the F and T gates, in the resist coating process, the resist film in the area where the FET was to be formed was It becomes possible to apply thinly and uniformly, and it is possible to obtain FgT with a narrow gate electrode. As a result, a high-speed, high-gain receiving DEIC can be manufactured with a high yield of 9. In addition, since no inverted mesa is formed in the peripheral stepped portion of the PD, resist coverage is improved, and characteristic defects such as short circuits in the PD portion due to leftover electrodes are reduced, which improves the yield of 0EIC. It's also effective.
第1図(a)は本発明の一実施例による受信0gICを
示す上面図、第1図Φ)はFET作製工程におけるフォ
トレジスト塗布時のレジストの流れを示す上面図、第2
図(a) 、 (b)はそれぞれ従来の受信用0fEI
cの上面図及びA−A’、B−B’断面図、第2図(C
)は従来の受信用0BICのFET作製工程におけるレ
ジストの流れを示す上面図である。
1・・・・半絶縁性GaAs基板、 2・・・・ゲート
電極、3−・−・ソース電極、4Φ・番・ドレイン電極
、5・・拳・FET部、 6・・−・PD部、7・・・
・Stイオン注入によるn型領域、8・自・・バッファ
層、9・・・・n型InGaAs受光層、1Qeess
n型InP層、11・・・・p型拡散領域、12・・・
・PDのp電極。
第 1 図(a)
第 1 図(b)Figure 1(a) is a top view showing a receiving 0g IC according to an embodiment of the present invention, Figure 1(a) is a top view showing the flow of resist during photoresist application in the FET manufacturing process,
Figures (a) and (b) are respectively 0fEI for conventional reception.
c top view and AA', BB' sectional views, Fig. 2 (C
) is a top view showing the flow of resist in the FET manufacturing process of a conventional receiving OBIC. DESCRIPTION OF SYMBOLS 1...Semi-insulating GaAs substrate, 2...Gate electrode, 3--Source electrode, 4Φ/drain electrode, 5...Fist/FET section, 6...-PD section, 7...
・N-type region by St ion implantation, 8. Self-buffer layer, 9..-n-type InGaAs light-receiving layer, 1Qeess
n-type InP layer, 11... p-type diffusion region, 12...
・PD p electrode. Figure 1 (a) Figure 1 (b)
Claims (1)
半導体基板上に集積され、該受光用フォトダイオード部
は前記電界効果トランジスタより突出して島状に形成さ
れた受信用光電子集積回路において、前記島状のフォト
ダイオード部の形状が、前記電界効果トランジスタのゲ
ートの長手方向に対し±45゜またはこれに近い角度傾
いた各々2組の直線で囲まれた矩形をなすことを特徴と
する受信用光電子集積回路。In a receiving optoelectronic integrated circuit in which a light receiving photodiode and a field effect transistor are integrated on the same semiconductor substrate, and the light receiving photodiode portion is formed in an island shape protruding from the field effect transistor, the island shaped photodiode A receiving optoelectronic integrated circuit characterized in that the shape of the part is a rectangle surrounded by two sets of straight lines each inclined at an angle of ±45° or close to the longitudinal direction of the gate of the field effect transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26703289A JPH03126258A (en) | 1989-10-12 | 1989-10-12 | Optoelectronic integrated circuit for reception |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26703289A JPH03126258A (en) | 1989-10-12 | 1989-10-12 | Optoelectronic integrated circuit for reception |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03126258A true JPH03126258A (en) | 1991-05-29 |
Family
ID=17439104
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26703289A Pending JPH03126258A (en) | 1989-10-12 | 1989-10-12 | Optoelectronic integrated circuit for reception |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03126258A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5708292A (en) * | 1995-08-29 | 1998-01-13 | Matsushita Electronics Corporation | Power amplification circuit |
-
1989
- 1989-10-12 JP JP26703289A patent/JPH03126258A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5708292A (en) * | 1995-08-29 | 1998-01-13 | Matsushita Electronics Corporation | Power amplification circuit |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2004511913A (en) | Single integrated E / D mode HEMT and manufacturing method thereof | |
JPH02257618A (en) | Semiconductor device and its manufacture | |
US4507845A (en) | Method of making field effect transistors with opposed source _and gate regions | |
JP3253824B2 (en) | GaAs semiconductor power device operable at low power supply voltage and method of manufacturing the same | |
JPH03126258A (en) | Optoelectronic integrated circuit for reception | |
CA1271850A (en) | Method for fabricating a field-effect transistor with a self-aligned gate | |
JPH01109764A (en) | Optoelectronic integrated circuit | |
JP2510544B2 (en) | Manufacturing method of monolithic microwave IC | |
JP3190705B2 (en) | Method for forming semiconductor quantum wires | |
KR100230744B1 (en) | Method of manufacturing a semiconductor device | |
JP3378561B2 (en) | Method for manufacturing semiconductor device | |
JP3283581B2 (en) | Method of forming resistor | |
JPH05190574A (en) | Field effect transistor | |
JP3203366B2 (en) | Field effect transistor | |
JP2868771B2 (en) | Method of forming alignment mark for electron beam exposure | |
JPH04206839A (en) | Semiconductor device and its manufacture | |
JPH01144684A (en) | Manufacture of schottky barrier junction gate type field-effect transistor | |
JPH0661545A (en) | Manufacture of hall element | |
JPS5892269A (en) | Field effect transistor | |
JPS61150379A (en) | Manufacture of semiconductor device | |
JPS6238881B2 (en) | ||
JP2825284B2 (en) | Method for manufacturing semiconductor device | |
JPH04364046A (en) | Semiconductor device | |
JPH05315299A (en) | Manufacture of semiconductor device | |
JPH04279035A (en) | Manufacture of field-effect-transistor |