JPH03126258A - Optoelectronic integrated circuit for reception - Google Patents

Abstract

PURPOSE:To make it possible to make thin and uniform the thickness of a resist in a part wherein FET is to be formed, even when an insular photodiode(PD) element has a stepped part, by forming the peripheral part of the PD element to be a rectangle surrounded by two sets of lines so extending as to form prescribed angles to the direction of the gate of the FET respectively. CONSTITUTION:An insular PD element 6 has a rectangle surrounded by lines forming angles of + or -45 deg. or approximating thereto to the longitudinal direction of a gate electrode 2, i.e., the direction of the width of a gate, of FET 5. When an optoelectronic integrated circuit(OEIC) is manufactured by using a (100) GaAs substrate 1, in this case, the direction of the gate width of the GaAs.FET 5 is set at [01-1] generally. Accordingly, the PD element 6 is formed by removing crystals for PD of InP, InGaAs and the like on the GaAs substrate 1 by a prescribed technique of photoengraving or etching so that the element is shaped in an island surrounded by two sets of lines in the direction of [001] or [0-11] forming an angle of 45 deg. to the above direction.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a receiving optoelectronic integrated circuit (hereinafter abbreviated as QEIC), and in particular to a light receiving element such as an InGaAs-PIN photodiode and a GaAs field effect transistor (hereinafter abbreviated as QEIC). This relates to an 0IIC that integrates FETs.

[Conventional technology]

FIG. 2(a) shows, for example, the conventional 1H shown in the following document.
It is a top view showing a receiving 0BIC that integrates G4As 7 Otodiodes and GaAa FETs, and the second publication) is a top view showing a schematic combination of the A-A' and B-B' cross sections of al. In the figure, 1 is Ga
PS substrate, 2 is a gate electrode of GaAB-FBT, 3 is a source electrode, 4 is a drain electrode, and 5 is an FgT section.

Further, 6 is an InGaAs-PD (photodiode) part, 7 is an n-type region, 8 is a buffer layer, and 9 is an n-type 1nGaA
6 is a light-receiving layer, 101'tn type InP window layer, 11 is a p-type scattering region, and 12 is a pm pole of PD6.

Here, the light absorbed in the pn junction depletion layer in the pn junction depletion layer 9 in the n-type InGaA3 light-receiving layer 9 generates electron-hole pairs, and the generated current flows as a signal to the external resistance. The potential is applied as a signal to the gate electrode 2 to increase the width of the FET section 5 by one width.

In this conventional 0EIC configuration, the GaAs substrate 1
A buffer layer 8 is interposed thereon to lower the dislocation density,
MOCVD of InP-based materials such as InGaAs and InP
After sequential crystal growth by a method such as a method, the InP-based material is removed leaving 20 parts 6 in the form of islands, and after exposing the GaAs substrate 1, the FET 5 is formed in this part.

At this time, the longitudinal direction (gate width direction) of the gate electrode 2 of the FIST 5 is generally set in the [011] direction when a (100) substrate is used as the substrate.

In addition, the shape of the island-like 20 parts 6 is [011], [011]
The rectangle surrounded by two sets of lines in each direction is 0F2I.
This is advantageous from the standpoint of effective use of the C chip area, and was the case with conventional 0EICs. The above document includes IEEE Transaction on Electron Device (Transaction on Electron Device).
Ron Devices).

VOL, 35, Gen. 8.1284 (1988).

[Problem to be solved by the invention]

Since the conventional receiving 0EIC is configured as described above and the difference in level between the 20 part 6 and the FET part 5 is as large as 5 to 10 μm, in the manufacturing process of Flil:T,
In the resist coating process of the photolithography process for the source and drain electrodes 3 and 4 and the gate electrode 2, resist accumulation υ occurs around the 20 part 6, resulting in so-called coating unevenness, where thick resist areas and thin resist areas are created. Cheap. Therefore,
There is a problem in that it is difficult to form a fine pattern of 1 μm or less near the PD section, and it is difficult to improve performance such as increasing the speed and gain of the OE process.

Also, when etching the steps around the 20 part 6, FE
One step between the gate direction of T5 and the direction perpendicular to the gate becomes a forward mesa, but the other step becomes a reverse mesa, which deteriorates the coverage of the resist. There were also problems such as the electrode remaining in this area.

The present invention has been made to solve the above-mentioned problems, and even if there is a step difference in the Q, PD section, the resist thickness in the part where the FET is to be formed can be formed thin and uniformly, and this can be achieved by It is an object of the present invention to obtain a receiving OGRC that can obtain a high-performance FIT even if the distance between the PD section and the FET section is shortened.

[Means to solve the problem]

The receiving 0EIC according to the present invention has a rectangular shape in which the periphery of the island-shaped PD section is surrounded by two sets of lines each forming an angle of ±45° or close to this with respect to the FIET gate direction. It was formed in

[Effect]

In the present invention, ±
A rectangular island PD surrounded by lines forming an angle close to 45°
F
The thickness of the resist in the portion where gT is to be formed can be made uniformly thin.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1(a) shows a receiving og IC according to an embodiment of the present invention.
FIG. In FIG. 1(a), 1 is a semi-insulating GaAs substrate, 2 is a gate electrode of a GaAs*FET, 3 is a source electrode, 4 is a drain electrode, and 5 is a FET.
Sections and 6 are island-shaped InGaAs-PD sections. Here, the island-like PD portion 6 is ±4 as shown in the figure with respect to the longitudinal direction of the gate electrode 2 of the FET 5, that is, the gate width direction.
It has a rectangle surrounded by lines forming an angle of 5° or close to this. At this time, when producing this type of 0FIC using the (100) GaAs substrate 1, GaAs-FE
The gate width direction of T 5 is set to [011] -
Boat fishing. Therefore, the 20 part 6 of this example makes an angle of 45° with respect to [001] or [011
] Ga is formed into an island shape surrounded by two sets of lines in the direction
It is formed by removing PD crystals such as IHP, InGaAs, etc. on the PS substrate 1 using predetermined photolithography and etching techniques. In the drawings, the same reference numerals indicate the same or corresponding parts.

In the receiving 0EIC according to this embodiment, FET5
When applying resist in the process of forming the gate electrode 2 and source-drain electrodes 3.4, the resist flow (direction of the arrow) 21 observed in the conventional 0ErC as shown in FIG. It is not blocked by the step in section 6,
Smooth resist flow 21 as shown in Figure 1(b)
is obtained, and a thin resist film of, for example, about 1 μm can be uniformly applied to a portion close to the PD section 6.

Therefore, in order to increase the speed and gain of GaAs mFET, the gate length must be made as small as possible, for example, 1 μm.
Although the following fine patterning is required, by using the present invention, even if the PD section 60 has a step difference of about 5 μm,
A fine pattern with a gate length of about 1 μm can be sufficiently formed at a short distance of about 50 μm from the PD.

Also, the area around the PD section 6 is (001) or [:011]
These surfaces do not form an inverted mesa even when etched with an anisotropic InP-based material etching solution, such as a Br-methanol solution.
It is possible to form a step substantially perpendicular to the substrate. Therefore, the covering of the resist around the PD section 6 is better than when there is a reverse mesa, and when forming a gate electrode by the lift-off method, electrode metal residue is generated, which is a step difference in the conventional reverse mesa. The problem of 0EIC is also solved.

In this example, GaAs-FE is formed on the GaAs substrate.
0EIC for reception integrated with T and InGaAs @PD
In the example shown above, InGaAs on a Si substrate
mPD and Si@MO8FET were integrated. GaAs llFET and InGaAS on grc or InP substrate
IPD was accumulated. Needless to say, this can also be applied to grc.

〔Effect of the invention〕

As described above, according to the present invention, the PD section with a step can be
Since the island shape was formed into a rectangular shape surrounded by lines forming an angle of approximately ±45° with respect to the longitudinal direction of the F and T gates, in the resist coating process, the resist film in the area where the FET was to be formed was It becomes possible to apply thinly and uniformly, and it is possible to obtain FgT with a narrow gate electrode. As a result, a high-speed, high-gain receiving DEIC can be manufactured with a high yield of 9. In addition, since no inverted mesa is formed in the peripheral stepped portion of the PD, resist coverage is improved, and characteristic defects such as short circuits in the PD portion due to leftover electrodes are reduced, which improves the yield of 0EIC. It's also effective.

[Brief explanation of the drawing]

Figure 1(a) is a top view showing a receiving 0g IC according to an embodiment of the present invention, Figure 1(a) is a top view showing the flow of resist during photoresist application in the FET manufacturing process,
Figures (a) and (b) are respectively 0fEI for conventional reception.
c top view and AA', BB' sectional views, Fig. 2 (C
) is a top view showing the flow of resist in the FET manufacturing process of a conventional receiving OBIC. DESCRIPTION OF SYMBOLS 1...Semi-insulating GaAs substrate, 2...Gate electrode, 3--Source electrode, 4Φ/drain electrode, 5...Fist/FET section, 6...-PD section, 7...
・N-type region by St ion implantation, 8. Self-buffer layer, 9..-n-type InGaAs light-receiving layer, 1Qeess
n-type InP layer, 11... p-type diffusion region, 12...
・PD p electrode. Figure 1 (a) Figure 1 (b)

Claims (1)

[Claims] In a receiving optoelectronic integrated circuit in which a light receiving photodiode and a field effect transistor are integrated on the same semiconductor substrate, and the light receiving photodiode portion is formed in an island shape protruding from the field effect transistor, the island shaped photodiode A receiving optoelectronic integrated circuit characterized in that the shape of the part is a rectangle surrounded by two sets of straight lines each inclined at an angle of ±45° or close to the longitudinal direction of the gate of the field effect transistor.