JPH05315299A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device manufacturing method by which the tapered shape of a semiconductor substrate can be formed with high reproducibility, the tapered section of the substrate can be formed to a gentle slope on which uniform gate electrodes can be easily formed, and the surface of the substrate in the area to be protected during the manufacturing process can be protected from oxidation or fine etching. CONSTITUTION:After a GaA As substrate 2 is etched to a prescribed depth by using an SiNx insulating film 3 which is etched by using a resist pattern 4 as a mask and has an adhesive property to the substrate 2 higher than the pattern 4 has as a mask, a process for side-etching the film 3 by prescribed dimensions by using the pattern 4 as a mask is repeated two or more times.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an FET (field effect transistor) including a compound semiconductor substrate manufactured by epitaxial growth.
The present invention relates to a method for manufacturing a semiconductor device such as a transistor) or an IC.

[0002]

2. Description of the Related Art A general manufacturing process of a low noise FET HEMT (high electron mobility transistor) will be described with reference to FIG. The left column of FIG. 4 is a plan view, and the right column of FIG. 4 is the plan view A of the left column.
FIG.

First, as shown in FIG. 4 (a), the semi-insulating Ga
On the As substrate 1, the active layer 2 having a thickness of 5500Å is formed by using the MBE (Molecular Beam Epitaxial) growth method.

Next, as shown in FIG. 4B, unnecessary active layer regions 7 are removed by etching in order to separate the active layer 2 between chips and to realize a predetermined device structure.

Next, as shown in FIG. 4C, an ohmic electrode 8 is formed on the active layer 2.

Next, as shown in FIG. 4D, the active layer 2 between the ohmic electrodes 8 and 8 is recess-etched to form a recess 5, and then the gate electrode 6 is formed in the recess 5. To do.

Thereafter, wiring electrodes, bonding electrodes, etc. are formed in order to obtain a predetermined device structure, but detailed description thereof will be omitted.

During the HEMT manufacturing process, as shown in FIG.
The active layer separating step (so-called mesa etching step) corresponding to the above will be sequentially described for the first conventional example shown in FIG. 5 and the second conventional example shown in FIG.

In the first conventional example, as shown in FIG.
First, the thickness d1 formed on the semi-insulating GaAs substrate 51 =
Active layer 52 consisting of 5500Å GaAs and AlGaAs
A SiNx film 53 having a thickness of about 1000Å is formed on the GaAs surface by the plasma CVD method.

Next, as shown in FIG. 5B, the SiNx film 5
5 (c) after applying the resist film 54 on the entire upper surface of FIG.
As shown in FIG. 3, the resist film 54 is exposed to form a resist pattern 54 having a predetermined pattern.
Next, as shown in FIG. 5D, the resist pattern 5
4 is used as a mask to selectively etch the SiNx film,
The active layer 52 is exposed.

Thereafter, as shown in FIG. 5 (e), the active layer 52 is d2 = 6000Å using a phosphoric acid type etchant.
Is etched to the depth of, and the unnecessary active layer region 55 is removed.

On the other hand, in the second conventional example, as shown in FIG. 6A, first, the thickness formed on the semi-insulating GaAs substrate 61.
A resist film 64 is applied to the entire GaAs surface of the active layer 62 made of GaAs and AlGaAs with d1 = 5500Å.
Then, as shown in FIG. 6B, the resist film 64 is exposed to a predetermined pattern to form the resist film 64 into a resist pattern 64. Next, the resist pattern 64 is post-baked in order to control the adhesion between the active layer 62 and the resist pattern 64. Next, as shown in FIG. 6C, the active layer 62 and the GaAs substrate 61 are removed by using a phosphoric acid-based etchant with the resist pattern 64 as a mask.
Etching is performed to a depth of 2 = 6000Å to remove the unnecessary active layer region 65.

[0013]

In the first conventional example shown in FIG. 5, the SiNx film 53, which has stronger adhesion to the active layer 52 than the resist 54, is used as an etching mask for the active layer 52. Therefore, the SiNx film 53, which is an insulating film, is formed on the surface of the active layer 52 which is susceptible to oxidation and minute etching during the manufacturing process, in addition to obtaining a highly reproducible etching shape with less variation. Active layer 5
2 has the advantage of being able to measure the surface stabilization.

However, in the first conventional example, the GaAl
Since the adhesiveness between the As active layer 52 and the SiNx film 53 is strong, it is difficult for the etchant to enter from between the active layer 52 and the SiNx film 53 during the etching of the active layer 52, as shown in FIG. 7 (a). The inclination angle θ of the side surface of the active layer 52 becomes larger than 45 °. This FIG. 7 corresponds to the BB cross section in the plan view of the left column of FIG. In FIG. 7 (a), Dz
= 6000Å, Lz = 3000Å, θ = 63 °. That is, the inclination of the side surface of the active layer 52 becomes very steep. Therefore, after that, for example, in the gate electrode forming step corresponding to FIG. 4D, when the resist 71 is applied on the active layer 52 as shown in FIG.
Thickness uniformity is reduced. That is, the thickness of the resist 71 becomes thinner at the X portion and becomes thicker at the Y portion. Then, when the resist 71 is exposed, the X portion is overexposed, while the Y portion is underexposed. As a result, the resist opening size in the X portion after development is enlarged, while it is reduced in the Y portion. Therefore, there is a problem that the gate electrode size is enlarged in the X portion, while the gate electrode size is reduced and the wire is broken in the Y portion.

FIG. 9 shows an enlarged view of the K portion of the BB cross section of FIG. 4 (d). The E section in FIG. 9 corresponds to the X section in FIG. 7, and the F section in FIG. 9 corresponds to the Y section in FIG. 7. According to the first conventional example, the gate electrode 6 expands at the E portion in FIG. 9 and the gate electrode 6 shrinks at the F portion in FIG.

In particular, when the gate length is shortened as the performance of the low noise FET is improved and the resist film thickness is further reduced, the above-mentioned nonuniformity of the gate electrode size is caused.

In the second conventional example shown in FIG. 6, since the resist 64 having a relatively weak adhesion to the GaAlAs active layer 62 is used as an etching mask for the active layer 62, the active layer 62 and the resist 64 are used. The etchant easily enters from between the active layer 62 and the active layer 62, as shown in FIG.
The inclination angle θ of the side surface becomes smaller than 45 °. That is, the inclination of the side surface of the active layer 62 becomes gentle. This Figure 8
Corresponds to the BB cross section in the plan view of the left column in FIG. 4. In the second conventional example, unlike the first example, the side surface of the active layer 62 has a gentle slope, so that the resist thickness for forming the gate electrode does not become relatively nonuniform, which causes nonuniform gate electrode dimensions. Never.

However, in the second conventional example, the resist 6
Since the adhesiveness between the resist 64 and the active layer 62 greatly changes depending on the post-baking condition of No. 4 and the surface state of the active layer 62, the active layer 62 by etching using the tapered resist 64 on the side surface of the active layer 62 as a mask. There is a problem that the reproducibility of the etched shape is very poor and the shape of the active layer 62 greatly varies.

For example, the dimensions Dv = 6000Å, Lv = 12000Å, θ of the inclined portion including the active layer 62 shown in FIG. 8A.
Even if the etching conditions are set with a design center value of = 26 °, inclination from Lv = 6000Å, θ = 45 ° shown in FIG. 8 (b) to Lv = 20000Å, θ = 17 ° shown in FIG. 8 (c) The shape of the part varies.

Further, unlike the first conventional example, the second conventional example does not have a SiNx film as a protective film for covering the active layer 62, so that the surface of the active layer 62 covered with the resist pattern 64 during the manufacturing process. There is also a problem that the surface of the active layer 62 becomes unstable due to oxidation and minute etching.

Therefore, an object of the present invention is to form a taper shape of a semiconductor substrate with good reproducibility, and to make the taper portion of the substrate have a gentle inclination which facilitates formation of a uniform gate electrode, and further, during the manufacturing process. Another object of the present invention is to provide a method of manufacturing a semiconductor device, which can protect the surface of a semiconductor substrate in a region to be protected from oxidation and minute etching.

[0022]

In order to achieve the above-mentioned object, the present invention provides a method in which, before forming a resist film on a semiconductor substrate, the adhesiveness to the semiconductor substrate is higher than that to the resist film on the semiconductor substrate. A high insulating film is formed, then the resist film is formed on the insulating film, and the first step of forming the resist film into a resist pattern by lithography, and the insulating film is etched using the resist pattern as a mask. A second exposing the surface of the semiconductor substrate
Steps and etching the semiconductor substrate to a predetermined depth using the etched insulating film as a mask, then,
A third step of side-etching the insulating film by a predetermined dimension using the resist pattern as a mask, and the third step is repeated twice or more.

[0023]

According to the above-mentioned manufacturing method, since the insulating film having higher adhesiveness to the semiconductor substrate than the resist film is formed on the semiconductor substrate, the semiconductor substrate is protected against oxidation and minute etching during the manufacturing process. It is possible to protect the surface and reduce variations in device characteristics within a semiconductor substrate or between semiconductor substrates.

Since the semiconductor substrate is etched to a predetermined depth by using the insulating film as a mask, and then the third step of side-etching the insulating film by a predetermined dimension from both sides using the resist pattern as a mask is repeated. The base L of the tapered portion of the semiconductor substrate is increased by the side etching of the insulating film by a predetermined dimension, and the inclination of the tapered portion becomes gentle. Therefore, at the time of forming the gate electrode, the thickness of the resist formed on the tapered portion can be made uniform, overexposure and deficiency of the resist can be suppressed, and a gate electrode having a desired uniform shape can be easily formed on the tapered portion. Can be formed.

For example, the third including the above side etching
When the process is repeated three times, as shown in FIG. 3, as compared with the first conventional example in which the side etching is not performed, (L1 + L2
The base L is increased by + L3), and the inclination of the tapered portion becomes gentle.

Further, since the semiconductor substrate is etched using the insulating film, which has a better adhesiveness to the semiconductor substrate than the resist film, as a mask, it is possible to perform highly reproducible etching with a small variation in etching dimension. The taper shape of the substrate is formed with good reproducibility.

[0027]

The present invention will be described in detail below with reference to the embodiments shown in the drawings.

This embodiment is a low noise FET HEM.
The manufacturing method of T is the same as that of the manufacturing method of FIG.
Details of the active layer separation step (so-called mesa etching step) shown in FIG. 4B will be described with reference to FIGS. 1 and 2 correspond to the B-B sectional view of the plan view on the left side of FIG.

First, as shown in FIG. 1 (a), an active layer 2 made of GaAs and AlGaAs was epitaxially grown on a GaAs semiconductor substrate 1 by MBE to a thickness of Te = 5500Å by a plasma CVD method. , A SiNx film 3 which is an insulating film is formed to a thickness of Ts = 2000Å,
Then, a photoresist film 4 is applied on the entire upper surface of the SiNx film 3.

Next, as shown in FIG. 1B, the photoresist film 4 is exposed to form a resist pattern 4 having a predetermined pattern.

Next, as shown in FIG. 1C, the SiNx film 3 is selectively etched by using BHF (buffered hydrofluoric acid) with the resist pattern 4 as a mask.
The surface of the active layer 2 is exposed.

Next, as shown in FIG. 1D, the above-mentioned SiNx
Using the film 3 as a mask, a phosphoric acid-based etchant (H ₃ P
O ₄ : H ₂ O ₂ : H ₂ O = 3: 1: 50) is used to etch the active layer 2 to a depth D1 = 2000Å.

Next, as shown in FIG. 1 (e), the SiNx film 3 is side-etched by the amount L with BHF (buffered hydrofluoric acid) using the resist pattern 4 as a mask.
Side etch so that 1 = 3000Å.

Next, as shown in FIG. 2F, the active layer 2 is etched again to a depth D2 = 2000 Å using the phosphoric acid-based etchant with the SiNx film 3 as a mask.

Next, as shown in FIG. 2G, SiNx is formed by using BHF with the resist pattern 4 as a mask.
The film 3 is side-etched so that the side-etching amount L2 = 3000Å.

Next, as shown in FIG. 2 (h), the SiN
Using the phosphoric acid-based etchant with the x film 3 as a mask, the active layer 2 and the GaAs semiconductor substrate 1 have a depth D3 =
Etch only 1500Å.

Next, as shown in FIG. 2I, SiNx is formed by using BHF with the resist pattern 4 as a mask.
The film 3 is side-etched so that the side-etching amount L3 = 3000Å.

Next, as shown in FIG. 2 (j), the SiNx
Using the phosphoric acid-based etchant with the film 3 as a mask, the active layer 2 and the GaAs semiconductor substrate 1 have a depth D4 = 5.
Etch only 00Å.

FIG. 3 shows the tapered shape of the etched side surface of the active layer 2 formed by the above manufacturing process. As shown in FIG. 3, the total etching depth of the tapered portion D =
6000Å (D = D1 + D2 + D3 + D4 = 2000Å
+ 2000Å + 1500Å + 500Å), the total base length of the taper part L = 15000Å (L = La + L1 + L)
b + L2 + Lc + L3 + Ld = 1000Å + 3000Å +
1000 Å + 3000 Å + 750 Å + 3000 Å + 25
0 Å). As described above, according to the above embodiment, the active layer 2 having the thickness Te = 5500Å can be selectively separated.

According to the above embodiment, as shown in FIGS. 1D to 1I, the active layer 2 is etched using the SiNx film 3 as a mask, and then the SiNx film is patterned using the resist pattern 4 as a mask.
By repeating the step of side-etching the film 3 three times and alternately performing the etching of the active layer 2 and the side-etching of the SiNx film 3, as compared with the first conventional example in which the side-etching of the SiNx film 3 is not performed, The base length L of the tapered portion is increased by the amount of the three side etchings (L1 + L2 + L3), and the inclination of the tapered portion can be made gentle. Therefore, at the time of forming the gate electrode, the thickness of the resist formed on the tapered portion can be made uniform, overexposure and deficiency of the resist can be suppressed, and a gate electrode having a desired uniform shape can be easily formed on the tapered portion. Can be formed.

Further, since the SiNx film 3 having a stronger adhesion to the active layer 2 than the photoresist 4 is used as the etching mask for the active layer 2, the active layer 2 can be etched with good reproducibility, and the variation can be prevented. A small etching shape can be realized.

Further, during the manufacturing process shown in FIGS. 1 and 2, the SiNx film 3 having strong adhesion to the active layer 2 protects the surface of the active layer 2 against oxidation and minute etching.
The surface of the active layer 2 can be maintained in a good state.

Further, since the resist thickness for forming the gate electrode can be made uniform as described above, for example, in the case of using a three-layer resist process using EB direct writing in the gate electrode forming step in order to shorten the gate electrode length. , The lower layer resist included in the above three layer resist is thin.
Even in the case of (about 1000Å), it becomes possible to easily form a gate electrode having a desired uniform shape.

In the above embodiment, the active layer 2 is formed by 4
Although the etching is performed in stages, the active layer 2 may be etched in optimal stages according to the post-etching manufacturing process and design processing dimensions. Further, the present invention can be applied not only to the manufacturing process of the HEMT as the low noise FET of the above embodiment, but also to the active layer separating step of the epitaxially grown semiconductor substrate.

[0045]

As is apparent from the above description, in the method for manufacturing a semiconductor device of the present invention, an insulating film which is etched using a resist pattern as a mask and has a stronger adhesiveness with a semiconductor substrate than the resist pattern is used as a mask. , The semiconductor substrate is etched to a predetermined depth, and then the third step of side-etching the insulating film by a predetermined dimension using the resist pattern as a mask is repeated twice or more, so that the insulating film is side-etched by a predetermined dimension. The bottom L of the tapered portion of the semiconductor substrate can be increased by the amount of etching, and the inclination of the tapered portion can be made gentle. Therefore, at the time of forming the gate electrode, the thickness of the resist formed on the tapered portion can be made uniform, overexposure and deficiency of the resist can be suppressed, and a gate electrode having a desired uniform shape can be easily formed on the tapered portion. Can be formed.

Further, since the semiconductor substrate is etched by using the insulating film, which has better adhesiveness to the semiconductor substrate than the resist film, as the mask, it is possible to perform etching with high reproducibility with less variation in etching dimension. The taper shape of the substrate can be formed with good reproducibility.

Further, since the insulating film having higher adhesiveness to the semiconductor substrate than the resist film is formed on the semiconductor substrate, the surface of the semiconductor substrate can be protected against oxidation and minute etching during the manufacturing process, It is possible to reduce variations in device characteristics within a semiconductor substrate, between semiconductor substrates, and the like.

[Brief description of drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 3 is an enlarged view showing an etching cross-sectional shape according to the above embodiment.

FIG. 4 HE which is a low noise FET as a semiconductor device
It is the top view and sectional drawing which show the process flow of MT.

FIG. 5 is a cross-sectional view showing an active layer separation step of a HEMT that is a first conventional example.

FIG. 6 is a cross-sectional view showing an active layer separation step of a HEMT that is a second conventional example.

FIG. 7 is a sectional view showing an etching sectional shape according to the first conventional example.

FIG. 8 is a sectional view showing an etching sectional shape according to the second conventional example.

9 is an enlarged view of a B-B cross section of a K portion in FIG. 4 (d).

[Explanation of symbols]

 1 GaAs substrate 2 active layer 3 SiNx film 4 photoresist 5 recess 6 gate electrode 7 unnecessary active layer region 8 ohmic electrode

Claims (1)

[Claims] 1. An insulating film having higher adhesion to the semiconductor substrate than the resist film is formed on the semiconductor substrate before forming the resist film on the semiconductor substrate, and then the insulating film is formed on the insulating film. A first step of forming the resist film and making the resist film into a resist pattern by lithography; a second step of etching the insulating film using the resist pattern as a mask to expose the surface of the semiconductor substrate; and the etching Etching the semiconductor substrate to a predetermined depth by using the insulating film thus formed as a mask, and then side etching the insulating film by a predetermined dimension using the resist pattern as a mask. A method of manufacturing a semiconductor device, characterized in that the method is repeated twice or more.