JPH03125464A - Surface mounted package - Google Patents
Surface mounted packageInfo
- Publication number
- JPH03125464A JPH03125464A JP1263202A JP26320289A JPH03125464A JP H03125464 A JPH03125464 A JP H03125464A JP 1263202 A JP1263202 A JP 1263202A JP 26320289 A JP26320289 A JP 26320289A JP H03125464 A JPH03125464 A JP H03125464A
- Authority
- JP
- Japan
- Prior art keywords
- soldered
- terminals
- solder
- main body
- adjacent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 29
- 239000012212 insulator Substances 0.000 claims description 11
- 238000005476 soldering Methods 0.000 abstract description 14
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000003491 array Methods 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 239000012774 insulation material Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 6
- 239000006071 cream Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は電子機器等に表面実装（ＳＭＴ）される、半導
体、ハイブリッドＩＣ５抵抗アレーなどの複数個の半田
付端子をもった表面実装パッケージの構造に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the structure of a surface mount package having a plurality of solder terminals, such as a semiconductor or a hybrid IC5 resistor array, which is surface mounted (SMT) on an electronic device or the like. It is something.
従来の技術
第５図に示すように従来の表面実装パッケージ１は、角
形の本体２の中に、半導体、ハイブリッドＩＣ１抵抗ア
レーなどを構成し、その入出力用の半田付端子３が側方
に直線上に複数個配列された構造になっている。その半
田付端子３間ピッチは小型化のため２．６ ｍ１ＪＩ
、 １．２７ｍ７Ｎ 、０．１３１ｂＬＩとじだ２ ヘ
−ノ
いに低ピツチ化に進んでいる。また、半田付端子３は第
６図のごとくプリント基板５等に表面実装し、半田付は
強度を十分保持するために、絶縁体２の外側に出た部分
４でほぼ直角に曲げられ、さらにプリント基板５の表面
にそって平行に曲げられ半田付はストレート部６を構成
した形状になっている。BACKGROUND ART As shown in FIG. 5, a conventional surface mount package 1 includes a semiconductor, a hybrid IC 1, a resistor array, etc. in a rectangular main body 2, and solder terminals 3 for input/output are arranged on the side. It has a structure in which multiple pieces are arranged in a straight line. The pitch between the three soldering terminals is 2.6 m1JI for miniaturization.
, 1.27m7N, 0.131bLI Tojida 2 The pitch is becoming much lower. In addition, the soldered terminal 3 is surface-mounted on a printed circuit board 5, etc., as shown in FIG. It has a shape that is bent parallel to the surface of the printed circuit board 5 and forms a straight part 6 for soldering.
発明が解決しようとする課題
このような表面実装パッケージをプリント基板５に実装
し、半田デイツプ工法、又はリフロー半田付は工法など
によシ半田付けする場合、低ピツチの表面実装パッケー
ジになるほど第５図に示すように隣接半田付端子３間に
半田ブリッジ７が発生すると云う問題があった。そこで
本発明はこのような半田ブリッジによる隣接半田付端子
間の短絡を防止することを目的とする。Problems to be Solved by the Invention When such a surface mount package is mounted on a printed circuit board 5 and soldered using a solder dip method or a reflow soldering method, the lower the pitch of the surface mount package, the more As shown in the figure, there is a problem in that solder bridges 7 occur between adjacent solder terminals 3. Therefore, it is an object of the present invention to prevent short circuits between adjacent soldered terminals due to such solder bridges.
課題を解決するための手段
そしてこの目的を達成するために本発明は隣接する半田
付端子間に、位置する本体の側方に絶縁体を配置ｔ し
たものである。Means for Solving the Problems and To Achieve This Objective According to the present invention, an insulator is placed on the side of the main body located between adjacent solder terminals.
３ ・・−
作用
以上の構成とすれば半田付端子間に絶縁体を設けている
ので、半田デイツプ工法でプリント基板のランドにいず
れの方向から半田付する場合においても、絶縁体が隣接
半田付端子間の半田ブリッジを切る作用を行うので、確
実に半田ブリッジによる短絡を防止することが可能とな
る。また、リフロー工法においてもクリーム半田が溶融
した状態で、絶縁体によりクリーム半田が遮断され、半
田ブリッジによる短絡不良が発生しなくなる。また、絶
縁体は半田付端子が左右に変形するのも防止するので、
いずれの半田付端子もプリント基板のランドの中央に確
実に位置決めされ、バラツキのない半田付が行えるもの
となる。3...- If the above structure is used, an insulator is provided between the soldering terminals, so when soldering to the land of a printed circuit board from any direction using the solder dip method, the insulator will not interfere with the adjacent solder. Since it acts to cut off solder bridges between terminals, it is possible to reliably prevent short circuits caused by solder bridges. Also, in the reflow method, the cream solder is cut off by the insulator in a molten state, and short circuit failures due to solder bridges do not occur. The insulator also prevents the soldered terminal from deforming from side to side.
Each soldering terminal is reliably positioned at the center of the land of the printed circuit board, and soldering can be performed without variation.
実施例
本発明の一実施例について第１図ａ、ｂｉ用いて説明す
る。第１図ａ、ｂにおいて、表面実装パッケージ１１の
本体１２の内部に半導体、ハイブリッドＩＣ１抵抗アレ
ーなどの回路が構成され、両側方の直線部にｌｄその回
路からの入出力用の半日付端子１３が複数個引出されて
いる。この直線上の半田付端子１３は薄板をプレス加工
し２．５ｆｆＪ１．２７ｍｍ、 Ｏ，Ｂｍｍなどの等ピ
ンチで配列した構造になっている。また半田付端子１３
は第２図のプリント基板１５のランドに表面実装し半田
付するため、この第２図に示すように本体１２から外側
に出た部分１４でほぼ直角に曲げられ、その後さらにプ
リント基板１５の表面にそって平行に曲げられ半田付は
ストレート部１６を構成した形状になっている。本実施
例ではすべての隣接する半田付端子１３間に絶縁体より
なる突起１７を一体に形成したことを特徴とする。Embodiment An embodiment of the present invention will be described with reference to FIGS. 1a and 1b. In FIGS. 1a and 1b, a circuit such as a semiconductor or a hybrid IC 1 resistor array is configured inside the main body 12 of the surface mount package 11, and half-date terminals 13 for input/output from the circuit are provided on the straight parts on both sides. Multiple items have been pulled out. The soldering terminals 13 on this straight line are formed by pressing thin plates and are arranged in equal pinch sizes such as 2.5ffJ1.27mm, O, and Bmm. In addition, soldering terminal 13
is surface-mounted and soldered to the land of the printed circuit board 15 shown in FIG. The soldering part is bent parallel to the straight part 16. This embodiment is characterized in that protrusions 17 made of an insulator are integrally formed between all adjacent solder terminals 13.
第２図の突起１７は、本体１２とともに一般的な樹脂モ
ールドで形成されるもので、具体的には第３図に示すよ
うに半田付端子１３を中心にして、金型が上型１８と下
型１９に分割した構造にしたもので製造し、この場合は
下型１９部分のみで突起１了が形成できるよう考慮して
いる。The protrusion 17 shown in FIG. 2 is formed with a general resin mold together with the main body 12. Specifically, as shown in FIG. It is manufactured with a structure that is divided into a lower mold 19, and in this case, it is considered that the protrusion 1 can be formed only in the lower mold 19 portion.
そしてこの突起１７により、半田付時に隣接する半田付
端子１３間が半田ブリッジされるのを、５ ′＼−・
完全に防止することが出来る。This protrusion 17 can completely prevent solder bridging between adjacent solder terminals 13 during soldering.
なお半田付端子１３の形状は第４図ａ、ｂに示すように
単なる屈曲したものと平坦なものもあるが、その時にも
それらの図に示すように角柱状にしたり、平板状にした
りして半田ブリッジを防止するＯ
発明の効果
以上のように本発明は表面実装パッケージの隣接する半
田付端子間に絶縁体を設けたので、半田ディソプ工法で
プリント基板のランドにいずれの方向から半田付する場
合においても、絶縁体が隣接する半田付端子の半田ブリ
ッジを切る作用を行い、確実に半田プリフジによる半田
付端子間短絡を防止することが可能となる。また、リフ
ロー工法においてもクリーム半田が溶融した状態で、絶
縁体によりクリーム半田が遮断され、ブリッジによる短
絡が発生しなくなる。今後端子間ピッチが低ピツチにな
ればなるほど、このような半田ブリッジが増加するため
本発明は大きな効果を出すものと々る。また、絶縁体は
半田付端子が左右に変６ ・＼−７
形するのを防止することもできるので、いずれの半田付
端子もプリント基板のランドの中央に確実に位置決めで
き、バラツキのない半田付が行える。The shape of the soldering terminal 13 may be simply bent or flat as shown in Figures 4a and 4b, but it may also be prismatic or flat as shown in those figures. Effects of the Invention As described above, the present invention provides an insulator between adjacent solder terminals of a surface mount package, so it is not possible to solder from any direction to the land of a printed circuit board using the solder dispersion method. Even in this case, the insulator acts to cut the solder bridges between adjacent solder terminals, and it is possible to reliably prevent short circuits between the solder terminals due to solder prefixes. In addition, even in the reflow method, the cream solder is cut off by the insulator in a molten state, and short circuits due to bridges do not occur. As the pitch between terminals becomes smaller in the future, the number of such solder bridges will increase, so the present invention will be more effective. In addition, the insulator can prevent the soldered terminals from changing shape from side to side, so all soldered terminals can be reliably positioned in the center of the land on the printed circuit board, ensuring consistent soldering. Can be attached.
第１図ａ、ｂは本発明の一実施例の平面図と正面図、第
２図は半田付端子部を示す斜視図、第３図は樹脂モーｙ
ｖ Ｆの金型の断面図、第４図ａ、ｂは本発明の他の実
施例を示す斜視図、第５図、第６図は従来例の平面図と
部分断面図を示す。
１１・・・・・表面実装パッケージ、１２・・・・・・
本体、１３・・・・・半田付端子、１７・・・・・・突
起。Figures 1a and b are a plan view and a front view of an embodiment of the present invention, Figure 2 is a perspective view showing a soldered terminal portion, and Figure 3 is a resin model.
FIGS. 4a and 4b are perspective views showing another embodiment of the present invention, and FIGS. 5 and 6 are a plan view and a partial sectional view of a conventional example. 11...Surface mount package, 12...
Main body, 13...Solder terminal, 17...Protrusion.
Claims (1)
接する前記半田付端子間には、絶縁体を配置したことを
特徴とする表面実装パッケージ。A surface mount package characterized in that a plurality of solder terminals are provided on the sides of a main body, and an insulator is disposed between adjacent solder terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1263202A JPH03125464A (en) | 1989-10-09 | 1989-10-09 | Surface mounted package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1263202A JPH03125464A (en) | 1989-10-09 | 1989-10-09 | Surface mounted package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03125464A true JPH03125464A (en) | 1991-05-28 |
Family
ID=17386200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1263202A Pending JPH03125464A (en) | 1989-10-09 | 1989-10-09 | Surface mounted package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03125464A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02126390A (en) * | 1988-11-05 | 1990-05-15 | Oki Electric Ind Co Ltd | Bankbook/slip transaction device |
-
1989
- 1989-10-09 JP JP1263202A patent/JPH03125464A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02126390A (en) * | 1988-11-05 | 1990-05-15 | Oki Electric Ind Co Ltd | Bankbook/slip transaction device |
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