JPH04186665A - Integrated circuit package - Google Patents

Integrated circuit package

Info

Publication number
JPH04186665A
JPH04186665A JP2311318A JP31131890A JPH04186665A JP H04186665 A JPH04186665 A JP H04186665A JP 2311318 A JP2311318 A JP 2311318A JP 31131890 A JP31131890 A JP 31131890A JP H04186665 A JPH04186665 A JP H04186665A
Authority
JP
Japan
Prior art keywords
terminals
board
mounting
substrate
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2311318A
Other languages
Japanese (ja)
Inventor
Kimiyo Takahashi
高橋　公代
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2311318A priority Critical patent/JPH04186665A/en
Publication of JPH04186665A publication Critical patent/JPH04186665A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3415—Surface mounted components on both sides of the substrate or combined with lead-in-hole components

Landscapes

  • Mounting Of Printed Circuit Boards And The Like (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To make use of the area of the rear of a printed wiring board effectively and enable the high-density mounting by making at least two pieces the terminals for insertion in a substrate, out of a plurality of terminals for mounting on the substrate, and lengthening the terminals to such degree that other parts can be mounted between the bottom of a mold member and the printed board. CONSTITUTION:Out of a plurality of terminals, which are provided being bent in L shapes downward respectively at both sides of a rectangular box-shaped mold member 1, one terminal 8 each at the corners symmetrical across a point is made the one for insertion in a substrate, and the rest are made the terminals 9 for mounting on the substrate, and the respective lengths, for the terminal 8 for insertion in the substrate, to the thinned insertion part 8a and, for the terminal 9 for mounting on the substrate, to the foot 9a bent twice are taken large. Plural pieces each of pattern lands 4 in two rows and, at respective corners, insertion holes 5, so that they may be symmetrical across a point, are provided at the surface of the printed board 3, and pattern lands 4, wherein through insertion holes 5 are opened, are provided at the rear. A plurality of electronic parts 10a, 10b, and 10c can be mounted between the bottom of the mold material 1 and the surface of the printed board 3.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、モノリシックＩＣ、ハイブリッドＩＣなどに
用いられる集積回路パッケージに関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an integrated circuit package used for monolithic ICs, hybrid ICs, and the like.

（従来の技術） 近年、集積回路パッケージは、機器の小形化を実現する
ため、−層の高密度実装に適応できることが強く要望さ
れている。(Prior Art) In recent years, there has been a strong demand for integrated circuit packages to be adaptable to high-density packaging of -layers in order to realize downsizing of devices.

この種の従来の集積回路パッケージについて、一般の集
積回路に広く使用されるＤＩＬ（デュアルインライン）
パッケージを例として、第３図および第４図により説明
する。Regarding this kind of conventional integrated circuit package, DIL (Dual Inline), which is widely used in general integrated circuits,
This will be explained using FIGS. 3 and 4, taking a package as an example.

第３図（ａ）、　（、ｂ）、　（ｃ）および（ｄ）は、
それぞれＤＩＬパッケージの外観を示す斜視図、プリン
ト基板に実装した状態を示す断面図、実装するプリント
基板の表面図および裏面図である４ 第３図（ａ）において、ＤＩＬパッケージは、長方形箱
状のモールド材ｌの両側面に、それぞれ下方にＬ字状に
折り曲げられた複数の基板挿入用端子２が設けられてい
る。一方、第３図（Ｃ）および（ｄ）に示すように、上
記のＤＩＬパッケージを実装するプリント基板３は、裏
面に上記の基板挿入用端子２に対応する複数のはんだ付
は用のパターンランド４が形成され、これを貫通するよ
うに挿入孔５が設けられている。Figure 3 (a), (, b), (c) and (d) are
These are a perspective view showing the external appearance of the DIL package, a sectional view showing the state mounted on a printed circuit board, and a front view and a back view of the printed circuit board to be mounted. A plurality of board insertion terminals 2 each bent downward into an L-shape are provided on both sides of the molding material l. On the other hand, as shown in FIGS. 3(C) and (d), the printed circuit board 3 on which the above DIL package is mounted has a plurality of soldering pattern lands corresponding to the above board insertion terminals 2 on the back surface. 4 is formed, and an insertion hole 5 is provided so as to pass through this.

このように構成されたＤＩＬパッケージをプリント基板
３に実装するには、自動挿入機又は手作業により、Ｄ工
Ｌパッケージをプリント基板３の挿入孔５に挿入した後
、はんだ溶融槽などを通してパターンランド４にはんだ
６により電気的機械的に接続する。In order to mount the DIL package configured in this way on the printed circuit board 3, the D-L package is inserted into the insertion hole 5 of the printed circuit board 3 using an automatic insertion machine or manually, and then the pattern land is inserted through a solder melting bath or the like. 4 is electrically and mechanically connected by solder 6.

次に、薄形の機器によく使用される５ＯＰ（スモールア
ウトラインパワー）パッケージについて、第４図により
説明する。第４図（ａ）、　（ｂ）および（Ｃ）は、Ｓ
ＯＰパッケージの外観を示す斜視図、プリント基板に実
装した状態を示す断面図および実装するプリント基板の
平面図である。Next, a 5OP (small outline power) package, which is often used in thin devices, will be explained with reference to FIG. FIG. 4(a), (b) and (C) are S
They are a perspective view showing the appearance of the OP package, a cross-sectional view showing the state mounted on a printed circuit board, and a plan view of the printed circuit board on which it is mounted.

第４図（ａ）において、ＳＯＰパッケージは、長方形箱
状のモールド材１の両側面に、それぞれほぼ２字状に２
回折り曲げられた複数の基板装着用端子７が設けられて
いる。一方、第４図（Ｃ）に示すように、上記のＳＯＰ
パッケージを実装するプリント基板３は、その表面には
んだ付は用のパターンランド４が形成されている。In FIG. 4(a), the SOP package has two approximately two-character shapes on both sides of a rectangular box-shaped molding material 1.
A plurality of board mounting terminals 7 are provided which are bent. On the other hand, as shown in Figure 4(C), the above SOP
A printed circuit board 3 on which the package is mounted has pattern lands 4 for soldering formed on its surface.

このように構成されたＳＯＰパッケージを、プリント基
板３に実装するには、まず、プリント基板３のパターン
ランド４に、クリームはんだを塗布した後、自動装着機
によりパターンランド４上に装着する。次に、はんだリ
フロー炉などを通してパターンランド４のクリームはん
だを溶融すると、はんだ６によりプリント基板３に電気
的機械的に接続される。In order to mount the SOP package configured in this manner on the printed circuit board 3, cream solder is first applied to the pattern lands 4 of the printed circuit board 3, and then the SOP package is mounted onto the pattern lands 4 by an automatic mounting machine. Next, when the cream solder on the pattern land 4 is melted in a solder reflow oven or the like, it is electrically and mechanically connected to the printed circuit board 3 by the solder 6.

（発明が解決しようとする課題） しかしながら、上記の構成では、ＤＩＬパッケージおよ
びＳＯＰパッケージが共に、モールド材１とプリント基
板３の間に隙間がないため、この隙間に他の部品を実装
できず、高密度実装を制約するという問題があった。ま
た、ＤＩＬパッケージでは、プリント基板３のパターン
ランド４すべてに挿入孔５を設けるため、パターンラン
ド４の輪郭全体を占有するため、高密度実装を制約する
という問題もあった。(Problem to be Solved by the Invention) However, in the above configuration, since there is no gap between the mold material 1 and the printed circuit board 3 in both the DIL package and the SOP package, other components cannot be mounted in this gap. There was a problem in that it restricted high-density packaging. Further, in the DIL package, since the insertion holes 5 are provided in all of the pattern lands 4 of the printed circuit board 3, the entire outline of the pattern lands 4 is occupied, which poses a problem of restricting high-density mounting.

本発明は上記の問題を解決するもので、機器の小形化を
実現する高密度実装を可能とする集積回路パッケージを
提供するものである。The present invention solves the above-mentioned problems and provides an integrated circuit package that enables high-density packaging and realizes miniaturization of devices.

（課題を解決するための手段） 上記の課題を解決するため、本発明は、複数の基板装着
用端子の内、少くとも２本を基板挿入用端子とするとと
もに、モールド材１の底面とプリント基板３との間に他
の部品が実装できる程度に上記の端子を長くするもので
ある。(Means for Solving the Problems) In order to solve the above problems, the present invention uses at least two of the plurality of board mounting terminals as board insertion terminals, and also provides a printed circuit board with the bottom surface of the molding material 1. The terminal is made long enough to allow other components to be mounted between it and the board 3.

（作　用） 上記の構成により、モールド材１の底面とプリント基板
３との間に他の部品を実装できるので、高密度な実装が
可能となる。また、基板挿入用の端子用の挿入孔の数が
少なくなるので、プリント基板の裏面（部品挿入面でな
い側）の面積が有効に利用でき、高密度な実装が可能と
なる。(Function) With the above configuration, other components can be mounted between the bottom surface of the mold material 1 and the printed circuit board 3, so high-density mounting is possible. Furthermore, since the number of insertion holes for terminals for board insertion is reduced, the area of the back surface of the printed circuit board (the side other than the component insertion surface) can be used effectively, and high-density mounting is possible.

（実施例） 本発明の実施例２例について第１図および第２図により
説明する。(Example) Two examples of the present invention will be described with reference to FIGS. 1 and 2.

第１図（ａ）、　（ｂ）、　（ｃ）および（ｄ）は、第
１の実施例として、モノリシックＩＣに適用した集積回
路パッケージの外観を示す斜視図、これをプリント基板
へ実装した状態を示す断面図、実装するプリント基板の
表面図および裏面図である。Figures 1 (a), (b), (c), and (d) are perspective views showing the appearance of an integrated circuit package applied to a monolithic IC as a first embodiment, and a state in which this is mounted on a printed circuit board. FIG. 2 is a cross-sectional view showing a front view and a back view of a printed circuit board to be mounted.

第１図（ａ）において、本発明によるモノリシックＩＣ
は、長方形箱状のモールド材１の両側面にそれぞれ下方
にＬ字状に折り曲げて設けた複数の端子の内、点対称と
なる端部にそれぞれ１本の基板挿入用端子８に、その他
を基板装着用端子９とし、基板挿入用端子８は細くした
挿入部８ａまで、基板装着用端子９は２回折り曲げた足
部９ａまでのそれぞれ長さを大きくとっである。第１図
（ｃ）および（ｄ）にそれぞれ示すように、プリント基
板３の表面には２列にそれぞれ複数個のパターンランド
４と、それぞれの端に点対称になるように挿入孔５が設
けられており、裏面には上記の挿入孔５が貫通開口する
パターンランド４が設けられている。In FIG. 1(a), a monolithic IC according to the present invention
Out of a plurality of terminals bent downward into an L-shape on both sides of a rectangular box-shaped molded material 1, one board insertion terminal 8 is placed at each point symmetrical end, and the other terminals are bent downward into an L-shape. The board mounting terminal 9 has a large length up to the thin insertion part 8a, and the board mounting terminal 9 has a large length up to the twice-bent leg part 9a. As shown in FIGS. 1(c) and 1(d), a plurality of pattern lands 4 are provided in two rows on the surface of the printed circuit board 3, and insertion holes 5 are provided in point symmetry at each end. A pattern land 4 through which the insertion hole 5 described above is opened is provided on the back surface.

第１図（ｂ）に示すように、モールド材１の底面とプリ
ント基板３の表面との間に、複数個の電子部品１０ａ、
　１０ｂおよび１０ｃが実装できる。As shown in FIG. 1(b), a plurality of electronic components 10a,
10b and 10c can be implemented.

以上のように構成された集積回路パッケージの働きを説
明する。The function of the integrated circuit package configured as described above will be explained.

まず、プリント基板３の表面に形成されたパターンラン
ド４およびその中間に形成された配線パターンの電極部
（図示せず）にクリームはんだを塗布した後、自動装着
機により電子部品１０ａ、　ｌＯｂおよび１０ｃを、ま
た、自動挿入機によりモノリシツクエＣの基板挿入用端
子８を挿入孔５に挿通するように装着する。基板装着用
端子９は、クリームはんだが塗布されたパターンランド
４に装着される。この時、上記の基板挿入用端子８は、
基板装着用端子９が、パターンランド４上に正確に位置
するよう案内する。その後、はんだリフロー炉およびは
んだ溶融槽を通すと、表面のパターンランド４ではクリ
ームはんだが溶は基板装着用端子９の足部９ａと、また
、裏面のパターンランド４では、基板挿入用端子８の挿
入部８ａの突出部とはんだ６により電気的１機械的に接
続される。同時に第１図に示すように、モールド材１の
底面とプリント基板３との間に装着した電子部品１０ａ
、　ｊｏｂおよび１０ｃも実装される。First, cream solder is applied to the pattern land 4 formed on the surface of the printed circuit board 3 and the electrode portions (not shown) of the wiring pattern formed in the middle thereof, and then electronic components 10a, 1Ob, and 10c are placed by an automatic mounting machine. Also, the board insertion terminal 8 of the monolithic cable C is inserted into the insertion hole 5 using an automatic insertion machine. The board mounting terminal 9 is mounted on the pattern land 4 coated with cream solder. At this time, the board insertion terminal 8 is
The board mounting terminal 9 is guided so as to be accurately positioned on the pattern land 4. After that, when passed through a solder reflow oven and a solder melting tank, the cream solder melts on the pattern lands 4 on the front surface and on the feet 9a of the board mounting terminals 9, and on the pattern lands 4 on the back surface, it melts on the feet 9a of the board insertion terminals 8. The protruding portion of the insertion portion 8a and the solder 6 are electrically and mechanically connected. At the same time, as shown in FIG.
, job and 10c are also implemented.

以上のように本実施例によれば、集積回路パッケージと
プリント基板との隙間に他の電子部品か実装できるので
、プリント基板のスペースを有効に利用する高密度実装
により機器の一層の小形化が可能となる。As described above, according to this embodiment, other electronic components can be mounted in the gap between the integrated circuit package and the printed circuit board, so the device can be further miniaturized through high-density mounting that effectively utilizes the space on the printed circuit board. It becomes possible.

次に、第２の実施例についてハイブリッドＩＣを例とし
て第２図により説明する。Next, a second embodiment will be described with reference to FIG. 2, taking a hybrid IC as an example.

第２図（ａ）、　（ｂ）、　（Ｃ）および（ｄ）は、本
発明によるハイブリッドＩＣの外観を示す斜視図、これ
をプリント基板へ実装した状態を示す断面図、これを実
装するプリント基板を表面図およびその裏面図である。FIGS. 2(a), (b), (C), and (d) are a perspective view showing the external appearance of the hybrid IC according to the present invention, a sectional view showing the state in which it is mounted on a printed circuit board, and a printed circuit board on which this is mounted. FIG. 2 is a front view and a back view of the substrate.

第２図（ａ）および（ｂ）において、本実施例が第１図
に示した第１の実施例と異なる点は、ＩＣ基板１１の上
面および下面に、それぞれ複数個の電子部品１２と１３
、および１４ａと１４ｂを実装した点である。In FIGS. 2(a) and 2(b), the present embodiment is different from the first embodiment shown in FIG.
, and 14a and 14b are implemented.

その他は第１の実施例と変らないので、同じ構成部品に
は同一符号を付してその説明を省略する。Since the rest is the same as the first embodiment, the same components are given the same reference numerals and their explanations will be omitted.

以上のように構成されたパイブリッドＩＣの働きは、第
１の実施例と変らないので、その説明を省略する。The function of the hybrid IC configured as described above is the same as that in the first embodiment, so the explanation thereof will be omitted.

（発明の効果） 以上説明したように、本発明によれば、プリント基板に
実装する際に、集積回路パッケージとプリント基板との
隙間や裏面を利用して、他の電子部品が実装できるので
、プリント基板のスペースを有効に利用した高密度実装
により、機器の一層の小形化が可能となる。(Effects of the Invention) As explained above, according to the present invention, when mounting on a printed circuit board, other electronic components can be mounted using the gap or back surface between the integrated circuit package and the printed circuit board. High-density mounting that makes effective use of printed circuit board space allows devices to be made even more compact.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）、　（ｂ）、　（ｃ）および（（］）は、
本発明による第１の実施例を示す集積回路パッケージの
斜視図、プリント基板への実装状態を示す断面図、プリ
ント基板の表面図および裏面図、第２図（ａ）。 （ｂ）、　（ｃ：）および（ｄ）は、第２の実施例を示
す集積回路パッケージの斜視図、プリント基板への実装
状態を示す断面図、プリント基板の表面図および裏面図
、第３図（ａ）、　（ｂ）、　（ｃ）および（ｄ）は、
第１の従来例を示す集積回路パッケージの斜視図、プリ
ント基板への実装状態を示す断面図、プリント基板の表
面図および裏面図、第４図（ａ）、　（ｂ）および（Ｃ
）は、第２の従来例を示す集積回路パッケージの斜視図
、プリント基板への実装状態を示す断面図およびプリン
ト基板の表面図である。 １　・・・モールド材、　２，８　・・・基板挿入用端
子、　３　・・・プリント基板、　４　・・・パターン
ランド、　５　・・・挿入孔、　６　・・・はんだ、　
７，９　・・・基板装着用端子、８ａ・・・挿入部、　
９ａ・・・足部、ｌＯａ。 １０ｂ、　１０ｃ、　１２．１３．１４ａ、　１４ｂ　
川霧子部品、１１・・・　ＩＣ基板。 特許出願人　松下電器産業株式会社 第１図 第２図 第３図 （ｂ） 、１′、４　　・′１ ．１ （ｂ）Figure 1 (a), (b), (c) and ((]) are
FIG. 2(a) is a perspective view of an integrated circuit package showing a first embodiment of the present invention, a sectional view showing a mounting state on a printed board, a front view and a back view of the printed board; (b), (c:), and (d) are a perspective view of an integrated circuit package showing the second embodiment, a sectional view showing the mounting state on the printed circuit board, a front view and a back view of the printed board, and the third embodiment. Figures (a), (b), (c) and (d) are
A perspective view of an integrated circuit package showing the first conventional example, a cross-sectional view showing the mounting state on a printed circuit board, a front view and a back view of the printed circuit board, and FIGS. 4(a), (b), and (C).
) is a perspective view of an integrated circuit package showing a second conventional example, a cross-sectional view showing a mounting state on a printed board, and a surface view of the printed board. 1... Mold material, 2, 8... Terminal for board insertion, 3... Printed circuit board, 4... Pattern land, 5... Insertion hole, 6... Solder,
7, 9... Terminal for board mounting, 8a... Insertion part,
9a...foot, lOa. 10b, 10c, 12.13.14a, 14b
Kiriko Kawa parts, 11... IC board. Patent applicant Matsushita Electric Industrial Co., Ltd. Figure 1 Figure 2 Figure 3 (b), 1', 4 ・'1. 1 (b)

Claims (4)

【特許請求の範囲】[Claims] （１）少くとも２本の基板挿入用端子と複数の基板装着
用端子とを有し、且つ、上記の端子の長さを、実装時に
プリント基板との隙間に他の電子部品が実装できる程度
に長くしたことを特徴とする集積回路パッケージ。(1) It has at least two board insertion terminals and multiple board mounting terminals, and the length of the above terminals is such that other electronic components can be mounted in the gap between the printed board and the printed board during mounting. An integrated circuit package characterized by a long length. （２）基板挿入用端子が四隅のうちの対角の２本、又は
他の一つの隅を加えた３本、もしくは四隅全部の４本で
あることを特徴とする請求項（１）記載の集積回路パッ
ケージ。(2) The board insertion terminal according to claim (1), characterized in that there are two diagonal terminals among the four corners, three terminals in addition to one other corner, or four terminals in all four corners. integrated circuit package. （３）集積回路の形態が、モノリシックＩＣであること
を特徴とする請求項（１）記載の集積回路パッケージ。(3) The integrated circuit package according to claim (1), wherein the integrated circuit is in the form of a monolithic IC. （４）集積回路の形態が、ハイブリッドＩＣであること
を特徴とする請求項（１）記載の集積回路パッケージ。(4) The integrated circuit package according to claim (1), wherein the integrated circuit is a hybrid IC.
JP2311318A 1990-11-19 1990-11-19 Integrated circuit package Pending JPH04186665A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2311318A JPH04186665A (en) 1990-11-19 1990-11-19 Integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2311318A JPH04186665A (en) 1990-11-19 1990-11-19 Integrated circuit package

Publications (1)

Publication Number Publication Date
JPH04186665A true JPH04186665A (en) 1992-07-03

Family

ID=18015694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2311318A Pending JPH04186665A (en) 1990-11-19 1990-11-19 Integrated circuit package

Country Status (1)

Country Link
JP (1) JPH04186665A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023008344A1 (en) * 2021-07-29 2023-02-02 ローム株式会社 Power semiconductor module and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023008344A1 (en) * 2021-07-29 2023-02-02 ローム株式会社 Power semiconductor module and semiconductor device

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