JPH0312505U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a block diagram of a switched line phase shifter according to an embodiment of the invention, and FIG. 2 is a block diagram of a conventional switched line phase shifter. 1 in the diagram
is a dielectric substrate, 2 is an input/output line, 3 is a FET, 3
a is the source electrode of FET 3, 3b is the drain electrode, 3c is the gate electrode, 4 is the inductance line, 5 is the reference line, 6 is the delay line, 7 is the reference side bias circuit, 7a is the reference side gate bias line, 7
b is a reference side capacitor, 7c is a reference side bias terminal, 7d is a reference side ground terminal, 8 is a delay side bias circuit, 8a is a delay side gate bias line, 8b is a delay side capacitor, 8c is a delay side bias terminal,
8d is a delay side ground terminal. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] An input/output line formed of a strip line on a dielectric substrate, a semiconductor element disposed at the contact point of the input/output line, and an input/output line formed on the dielectric substrate for applying a bias voltage or bias current to the electrode of the semiconductor element. In a switched line type phase shifter, two RF switches each consisting of a bias circuit are connected to each other by a reference line consisting of a strip line and a delay line. A switched line phase shifter characterized in that the electrical lengths of the high-ass circuits on the line side and the delay line side are made unequal.