JPH0312502U

JPH0312502U -

Info

Publication number: JPH0312502U
Application number: JP7275989U
Authority: JP
Priority date: 1989-06-21
Filing date: 1989-06-21
Publication date: 1991-02-07

Description

[Brief explanation of drawings]

第１図は、この考案の一実施例によるスイツチ
ドライン型移相器の構成図、第２図は、従来のス
イツチドライン型移相器の構成図である。図中１
は誘電体基板、２は入出力線路、３はＦＥＴ、３
ａはＦＥＴ３のソース電極、３ｂはドレイン電極
、３ｃはゲート電極、４はインダクタンス用線路
、５は基準線路、６は遅延線路、７は基準側バイ
アス回路、７ａは基準側ゲートバイアス線路、７
ｂは基準側キヤパシタ、７ｃは基準側バイアス端
子、７ｄは基準側接地端子、８は遅延側バイアス
回路、８ａは遅延側ゲートバイアス線路、８ｂは
遅延側キヤパシタ、８ｃは遅延側バイアス端子、
８ｄは遅延側接地端子である。なお、図中同一符
号は同一、または相当部分を示す。 FIG. 1 is a block diagram of a switched line phase shifter according to an embodiment of the invention, and FIG. 2 is a block diagram of a conventional switched line phase shifter. 1 in the diagram
is a dielectric substrate, 2 is an input/output line, 3 is a FET, 3
a is the source electrode of FET 3, 3b is the drain electrode, 3c is the gate electrode, 4 is the inductance line, 5 is the reference line, 6 is the delay line, 7 is the reference side bias circuit, 7a is the reference side gate bias line, 7
b is a reference side capacitor, 7c is a reference side bias terminal, 7d is a reference side ground terminal, 8 is a delay side bias circuit, 8a is a delay side gate bias line, 8b is a delay side capacitor, 8c is a delay side bias terminal,
8d is a delay side ground terminal. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims

[Claims for Utility Model Registration] (1) An input/output line constituted by a strip line on a dielectric substrate, a semiconductor element disposed at the contact point of the input/output line, and a bias voltage or bias applied to the electrode of the semiconductor element. The above two R
A switched line phase shifter in which the output part of an F switch is connected by a reference line made of a strip line and a delay line, characterized in that the delay line and the bias circuit on the delay line side are brought close to each other. vessel. (2) An input/output line consisting of a strip line on a dielectric substrate, a semiconductor element arranged at the contact point of the input/output line, and a dielectric material for applying a bias voltage or bias current to the electrode of the semiconductor element. The above two R
A switched line type phase shifter in which the output part of an F switch is connected by a reference line constituted by a strip line and a delay line, characterized in that the delay circuit and the bias circuit on the delay line side are made close to each other as a meander line. dry line phase shifter.