JPH0336201U - - Google Patents
Info
- Publication number
- JPH0336201U JPH0336201U JP9727489U JP9727489U JPH0336201U JP H0336201 U JPH0336201 U JP H0336201U JP 9727489 U JP9727489 U JP 9727489U JP 9727489 U JP9727489 U JP 9727489U JP H0336201 U JPH0336201 U JP H0336201U
- Authority
- JP
- Japan
- Prior art keywords
- line
- lines
- strip
- bias voltage
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 2
- 230000001747 exhibiting effect Effects 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 1
Landscapes
- Waveguide Switches, Polarizers, And Phase Shifters (AREA)
Description
第１図は本考案の半導体移相器の一実施例を示
す斜視図、第２図は本考案の半導体移相器の他の
実施例を示す斜視図、第３図は従来の半導体移相
器の一例を示す斜視図である。
図において、１は半導体基板、２は地導体、３
は主線路、４は装荷線路、５は装荷線路短絡スタ
ブ、６は短絡用パツド、７はドレイン電極、８は
ゲート電極、９は共通ソース電極、１０はＦＥＴ
、１１は低インピーダンス線路、１２は高インピ
ーダンス、１３はバイアスパツド、１４はバイア
ス回路、１５は短絡用バイアホール、１６は開放
スタブ線路、１７は低インピーダンス線路、１８
は高インピーダンス線路、１９は接地用パツド、
２０は接地用回路である。なお、各図中同一符号
は同一または相当部分を示す。
FIG. 1 is a perspective view showing one embodiment of the semiconductor phase shifter of the present invention, FIG. 2 is a perspective view showing another embodiment of the semiconductor phase shifter of the present invention, and FIG. 3 is a conventional semiconductor phase shifter. It is a perspective view showing an example of a container. In the figure, 1 is a semiconductor substrate, 2 is a ground conductor, and 3
is the main line, 4 is the loading line, 5 is the loading line short-circuit stub, 6 is the short-circuit pad, 7 is the drain electrode, 8 is the gate electrode, 9 is the common source electrode, 10 is the FET
, 11 is a low impedance line, 12 is a high impedance line, 13 is a bias pad, 14 is a bias circuit, 15 is a shorting via hole, 16 is an open stub line, 17 is a low impedance line, 18
is a high impedance line, 19 is a grounding pad,
20 is a grounding circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
ツプ線路で構成される主線路と、上記主線路の両
端に各々並列に付加された同じくストリツプ線路
で構成される装荷線路と、各々の上記装荷線路に
並列に付加された同じくストリツプ線路で構成さ
れるスタブ線路と、各々の上記装荷線路の先端に
直列に接続された、印加直流バイアス電圧を変化
させることによつて異なるインピーダンスを呈す
る半導体素子と、上記半導体素子に直流バイアス
電圧を印加する手段を具備する半導体移相器にお
いて、上記スタブ線路の一部を金ワイヤあるいは
金リボン等で接地したことを特徴とする半導体移
相器。 (2) サブストレート基板上に形成されるストリ
ツプ線路で構成される主線路と、上記主線路の両
端に各々並列に付加された同じくストリツプ線路
で構成される装荷線路と、各々の上記装荷線路に
並列に付加された同じくストリツプ線路で構成さ
れるスタブ線路と、各々の上記装置線路の先端に
直列に接続された、印加直流バイアス電圧を変化
させることによつて異なるインピーダンスを呈す
る半導体素子と、上記半導体素子に直流バイアス
電圧を印加する手段を具備する半導体移相器にお
いて、上記スタブ線路の一部を短絡用バイアホー
ルで接地したことを特徴とする半導体移相器。[Claims for Utility Model Registration] (1) A main line consisting of a strip line formed on a substrate substrate, and a loaded line consisting of strip lines attached in parallel to both ends of the main line. and a stub line, also made up of a strip line, added in parallel to each of the above-mentioned loading lines, and connected in series to the tip of each of the above-mentioned loading lines, by varying the applied DC bias voltage. A semiconductor phase shifter comprising a semiconductor element exhibiting impedance and means for applying a DC bias voltage to the semiconductor element, wherein a part of the stub line is grounded with a gold wire or a gold ribbon. Partner. (2) A main line consisting of strip lines formed on the substrate board, loading lines also consisting of strip lines added in parallel to both ends of the main line, and each of the above loading lines. a stub line which is also formed of a strip line and which is added in parallel; a semiconductor element which exhibits a different impedance by changing the applied DC bias voltage and which is connected in series to the tip of each of the above device lines; 1. A semiconductor phase shifter comprising means for applying a DC bias voltage to a semiconductor element, characterized in that a part of the stub line is grounded through a shorting via hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9727489U JPH0336201U (en) | 1989-08-21 | 1989-08-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9727489U JPH0336201U (en) | 1989-08-21 | 1989-08-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0336201U true JPH0336201U (en) | 1991-04-09 |
Family
ID=31646422
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9727489U Pending JPH0336201U (en) | 1989-08-21 | 1989-08-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0336201U (en) |
-
1989
- 1989-08-21 JP JP9727489U patent/JPH0336201U/ja active Pending
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