JPH0312458B2 - - Google Patents

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Publication number
JPH0312458B2
JPH0312458B2 JP56215649A JP21564981A JPH0312458B2 JP H0312458 B2 JPH0312458 B2 JP H0312458B2 JP 56215649 A JP56215649 A JP 56215649A JP 21564981 A JP21564981 A JP 21564981A JP H0312458 B2 JPH0312458 B2 JP H0312458B2
Authority
JP
Japan
Prior art keywords
region
substrate
semiconductor substrate
conductivity type
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56215649A
Other languages
Japanese (ja)
Other versions
JPS58111369A (en
Inventor
Masami Yamaoka
Masaharu Toyoshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP21564981A priority Critical patent/JPS58111369A/en
Priority to EP82111854A priority patent/EP0083060B2/en
Priority to DE8282111854T priority patent/DE3276091D1/en
Publication of JPS58111369A publication Critical patent/JPS58111369A/en
Priority to US07/407,157 priority patent/US5596217A/en
Publication of JPH0312458B2 publication Critical patent/JPH0312458B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明はトランジスタ等に内蔵して使用可能
で、制御された降伏電圧をもつ過電圧保護素子を
含む半導体装置に関する。なお、ここでツエナー
ダイオードとはアバランシエ降伏等の降伏現象を
素子の機能として使用するダイオードの意味とす
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device including an overvoltage protection element that can be built into a transistor or the like and has a controlled breakdown voltage. Note that the Zener diode herein refers to a diode that uses a breakdown phenomenon such as avalanche breakdown as its element function.

従来、素子に内蔵して使用する過電圧保護素子
の一つである保護ダイオードは、ダイオードの降
伏電圧VZを保護すべきトランジスタのVCEO電圧
より低くするために種々の工夫を行つている。こ
のダイオードの形成方法としては、第1図中の丸
枠Aに示すように、不活性なベース領域の一部を
深く拡散してコレクタ高濃度層とのリーチスルー
によりVZを決定する方法があり、また第2図中
の丸枠Bに示すように、上記のものと同じく不活
性なベース領域の一部にイオン注入等で高精度に
制御したコレクタと同一導電型の高濃度領域を形
成してVZを決定する方法があり、また第3図中
の丸枠Cに示すように、横方向のチヤンネルスト
ツパとのリーチスルーを利用してVZを決定する
方法があり、また第4図中の丸枠Dに示すように
横方向でパンチスルーによりVZを決定させる方
法等がある。第5図に第1〜第4図に示す半導体
構造の等価回路を示す。なお、第1〜第4図中2
1はN型のコレクタ基体、22はN型のコレクタ
高濃度領域、23がP型ベース領域、23AはP
型のダイオード形成用拡散領域、24はN型エミ
ツタ領域、25はベース電極、26はエミツタ電
極、27はシリコン酸化膜、28はN型の高精度
拡散領域、29はP型の拡散領域である。
Conventionally, a protection diode, which is one of the overvoltage protection elements built into a device and used, has been devised in various ways to make the breakdown voltage V Z of the diode lower than the V CEO voltage of the transistor to be protected. As shown in the circle A in Figure 1, this diode can be formed by deeply diffusing a part of the inactive base region and determining V Z by reach-through with the collector high concentration layer. Also, as shown in circle B in Figure 2, a highly concentrated region of the same conductivity type as the collector is formed in a part of the inactive base region by ion implantation, etc., as shown in circle B in Figure 2. There is a method to determine V Z using As shown in the circle D in Fig. 4, there is a method of determining V Z by punch-through in the horizontal direction. FIG. 5 shows an equivalent circuit of the semiconductor structure shown in FIGS. 1 to 4. In addition, 2 in Figures 1 to 4
1 is an N-type collector substrate, 22 is an N-type collector high concentration region, 23 is a P-type base region, and 23A is a P-type collector substrate.
24 is an N-type emitter region, 25 is a base electrode, 26 is an emitter electrode, 27 is a silicon oxide film, 28 is an N-type high-precision diffusion region, and 29 is a P-type diffusion region. .

これらのうち、第1,2図に示す構造のみが製
品として確認されており、第3,4図に示す構造
のものは、案が示されているにすぎない。これは
第3,4図に示すものは基板表面に形成されるた
め、外部からの電荷の影響によりVZが大幅に変
動して全く使いものにならないためである。さて
第1,2図に示す構造については半導体基体内に
動作部があるためVZの変動は問題にならないが、
ダイオード部を形成するための工程が当然必要と
なり、コストアツプとなる。また内燃機関用点火
装置の点火コイル制御用に必要とされる360V±
10%のVZの制御が非常に困難で歩留り的にもコ
ストアツプとなる。第1,2図に示す構造のもの
は±25%程度がバラツキとして実測されている。
Of these, only the structures shown in FIGS. 1 and 2 have been confirmed as products, and the structures shown in FIGS. 3 and 4 are only proposed. This is because the devices shown in FIGS. 3 and 4 are formed on the surface of the substrate, and V Z changes significantly due to the influence of external charges, making them completely useless. Now, regarding the structure shown in Figures 1 and 2, since the operating part is inside the semiconductor substrate, fluctuations in V Z are not a problem.
Naturally, a process for forming the diode portion is required, which increases costs. In addition, the 360V± required for controlling the ignition coil of the ignition system for internal combustion engines
Controlling VZ of 10% is extremely difficult and increases cost in terms of yield. For the structures shown in Figures 1 and 2, it has been actually measured that the variation is approximately ±25%.

本発明は上記の点を考慮してなされたものであ
り、上記のものに比べて、比較的容易な製造手法
により得られ、特性の安定した、しかも制御性の
良い降伏電圧をもつ新規な過電圧保護素子を含む
半導体装置を提供することを目的とする。
The present invention has been made in consideration of the above points, and is a novel overvoltage that can be obtained by a relatively easy manufacturing method compared to the above, has stable characteristics, and has a breakdown voltage with good controllability. An object of the present invention is to provide a semiconductor device including a protection element.

本発明の基本的素子構造は、所定の導電型の半
導体基体と、前記半導体基体の一主表面に形成さ
れ、該基体の導電型と反対導電型の第1領域と、
前記半導体基体の一主表面に前記第1領域と離間
して形成され、該基体と同一導電型でかつ該基体
より高不純物濃度の第2領域と、前記第1領域及
び前記第2領域間の基体表面上の一部または全部
を絶縁膜を介して覆い、かつその少なくとも一部
が前記第1領域及び第2領域の一部と前記絶縁膜
を介して重なり合うように配置されたゲート電極
となる導電膜と、前記第1領域に電気接続したア
ノード電極と、前記半導体基体の裏面に電気接続
したカソード電極とを備え、前記ゲート電極と前
記アノード電極との間に所定の電位差を与えたこ
とを特徴とするものである。
The basic element structure of the present invention includes a semiconductor substrate of a predetermined conductivity type, a first region formed on one main surface of the semiconductor substrate and of a conductivity type opposite to that of the substrate;
a second region formed on one main surface of the semiconductor substrate apart from the first region and having the same conductivity type as the substrate and having a higher impurity concentration than the substrate; and a second region between the first region and the second region. A gate electrode covers a part or all of the surface of the substrate with an insulating film interposed therebetween, and at least a part thereof overlaps a part of the first region and the second region with the insulating film interposed therebetween. A conductive film, an anode electrode electrically connected to the first region, and a cathode electrode electrically connected to the back surface of the semiconductor substrate, and a predetermined potential difference is applied between the gate electrode and the anode electrode. This is a characteristic feature.

そこで、本発明の基本構造を第6図に示す基体
例を用いて説明する。N型の半導体基体1の一主
表面に(第1領域である)P型の領域2、N+
つまりN型の基体1より高不純物濃度をもつ(第
2領域である)領域3を形成し、これら表面をシ
リコン酸化膜等の絶縁膜4で覆い、領域2、領域
3、及び領域2,3で囲まれた基体表面上を絶縁
膜4上から領域2、領域3の少なくとも一部オー
バーラツプするように導電電極5で覆い、この電
極5をゲートGとする。基体1と領域2に適切に
電極6を設け、基体1に電気接続する電極をカソ
ードKとし、領域2に電気接続する電極をアノー
ドAとする。そして、このアノードAに逆バイア
スを印加し、ゲートGとアノードAとを第7図の
如く電源Sを介して接続する(この場合ゲート電
圧VG=0)、そこで逆バイアス電圧を上げていく
と、始めにゲートG下の基体表面に反転層7が形
成され領域2より領域3まで到達した状態にあ
る。この時点のゲート・基体間の電圧をVTとす
る。さらに逆バイアス電圧を上げてゆくと、この
反転層7が領域3より追い払われる形となり、反
転層7と領域3間の表面に空乏領域71ができ
(もちろん基体内のPN接合部の全てにできるが
説明上省略してある)、基体濃度で決まる電界強
度でアバランシエ降伏現象を引き起こす。このと
きの降伏電圧VZは必ず基体が本来有する耐圧
(VBLUK)よりも低く本発明者等の実験によれば1/
3程度となることが確認されており、素子保護用
の内蔵ダイオードとして好都合である。
Therefore, the basic structure of the present invention will be explained using an example of a substrate shown in FIG. On one main surface of the N-type semiconductor substrate 1, a P-type region 2 (first region) and a region 3 (second region) having a higher impurity concentration than the N + type, that is, the N-type substrate 1 are formed. Then, these surfaces are covered with an insulating film 4 such as a silicon oxide film, and the region 2, the region 3, and the substrate surface surrounded by the regions 2 and 3 are covered with at least a partial overlap of the regions 2 and 3 from above the insulating film 4. This electrode 5 is used as a gate G. Electrodes 6 are appropriately provided on the substrate 1 and the region 2, the electrode electrically connected to the substrate 1 is designated as a cathode K, and the electrode electrically connected to region 2 is designated as an anode A. Then, apply a reverse bias to this anode A, connect the gate G and the anode A via the power supply S as shown in Fig. 7 (in this case, the gate voltage V G =0), and then increase the reverse bias voltage. First, an inversion layer 7 is formed on the surface of the substrate under the gate G and reaches from region 2 to region 3. Let the voltage between the gate and the substrate at this point be V T . When the reverse bias voltage is further increased, this inversion layer 7 is driven away from the region 3, and a depletion region 71 is formed on the surface between the inversion layer 7 and the region 3 (of course, it is formed in all the PN junctions in the substrate). (omitted for the sake of explanation), causes an avalanche breakdown phenomenon with the electric field strength determined by the substrate concentration. The breakdown voltage V Z at this time is always lower than the withstand voltage (V BLUK ) originally possessed by the substrate, and according to the inventors' experiments, it is 1/
It has been confirmed that the diode is about 3, which is convenient as a built-in diode for protecting the device.

さらにVZの制御性については、最も関係する
と推定される領域3と領域2との離間距離に関し
て、耐圧を得るのに必要な一定の距離があれば、
残り部分には反転層7ができており、反転層内の
電圧は一定であるから、VZに関係しない。即ち、
本発明構造によれば領域2,3間の距離精度が要
求されず、この為従来構造に比べVZのバラツキ
は約1/5となる。この効果を反転層のバツフア効
果と呼ぶことにする。
Furthermore, regarding the controllability of V Z , if there is a certain distance necessary to obtain withstand voltage with respect to the distance between region 3 and region 2, which is estimated to be most relevant,
An inversion layer 7 is formed in the remaining portion, and since the voltage within the inversion layer is constant, it is not related to V Z . That is,
According to the structure of the present invention, distance accuracy between regions 2 and 3 is not required, and therefore the variation in V Z is about 1/5 compared to the conventional structure. This effect will be referred to as the buffer effect of the inversion layer.

さらに、動作部の表面は絶縁膜4を介して電極
5で必ずシールドされているため、外部からの電
荷の影響を受けることが無く、経時変化のない安
定した降伏電圧VZを得ることができる。また、
第3,4図に示す半導体構造では初期値に対して
2倍に達するVZの変動があるのに対し、本発明
構造ではVZの変動をほとんど皆無にできるとい
う利点がある。なお、半導体基体1や各領域2,
3の導電型を反対導電型とした場合にも本発明の
基本構造を達成できる。
Furthermore, since the surface of the operating part is always shielded by the electrode 5 via the insulating film 4, it is not affected by external charges and a stable breakdown voltage VZ that does not change over time can be obtained. . Also,
In the semiconductor structures shown in FIGS. 3 and 4, there is a variation in V Z that is twice the initial value, whereas the structure of the present invention has the advantage that the variation in V Z can be almost completely eliminated. Note that the semiconductor substrate 1 and each region 2,
The basic structure of the present invention can also be achieved when the conductivity type 3 is the opposite conductivity type.

以下、本発明を図示に示す実施例により詳述す
る。第6図において、半導体基体1はN型で濃度
は1.5×1014atms/cm3、領域2はP型の拡散層で
表面濃度は1×1018atms/cm3、層の深さは30μm
である。この領域2上に電極6を設けてダイオー
ド構造においてアノードAを構成している。領域
3はN型拡散層で表面濃度は2×1019atms/cm3
層の深さは18μmである。また絶縁膜4はSiO2
で、リンゲツタリングを行つており厚さ4.0μmで
ある。電極5,6はアルミニウムAlで厚さ4.0μm
であり、例えば内燃機関用点火装置などの出力用
トランジスタの如くトランジスタ保護用ダイオー
ドとして内蔵させる場合には、半導体基体1はコ
レクタに共通、領域2はベース、領域3はエミツ
タと同時に形成し、絶縁膜4はフイールドの
SiO2膜をそのまま使用し、電極もベース、エミ
ツタ電極と同時に形成でき、本発明素子をトラン
ジスタに内蔵させるにあたり特別の工程は全く不
要である。ここで通常ゲートGは領域2に直接
Al配線で接続するのが一般的であり、また領域
2とトランジスタのベース領域の不活性部を共通
としても良い。
Hereinafter, the present invention will be explained in detail with reference to embodiments shown in the drawings. In FIG. 6, semiconductor substrate 1 is an N-type diffusion layer with a concentration of 1.5×10 14 atms/cm 3 , and region 2 is a P-type diffusion layer with a surface concentration of 1×10 18 atms/cm 3 and a layer depth of 30 μm.
It is. An electrode 6 is provided on this region 2 to constitute an anode A in a diode structure. Region 3 is an N-type diffusion layer with a surface concentration of 2×10 19 atms/cm 3 ,
The depth of the layer is 18 μm. Further, the insulating film 4 is a SiO 2 film, subjected to ring etching, and has a thickness of 4.0 μm. Electrodes 5 and 6 are made of aluminum with a thickness of 4.0 μm.
For example, when a transistor is built in as a protection diode, such as an output transistor for an ignition device for an internal combustion engine, the semiconductor substrate 1 is formed in common with the collector, the region 2 is formed as the base, and the region 3 is formed simultaneously with the emitter, and is insulated. Membrane 4 is the field
The SiO 2 film can be used as is, and the electrodes can be formed at the same time as the base and emitter electrodes, and no special steps are required to incorporate the device of the present invention into a transistor. Here, normally gate G is directly connected to region 2.
It is common to connect with Al wiring, and region 2 and the inactive part of the base region of the transistor may be shared.

そこで、本発明構造に基づく作用を説明する。
半導体基体本来の耐圧VBLUKは約1000vであるが、
基体内にベース、エミツタをもつトランジスタの
VCEOは約400vである。本発明構造に基づく降伏
電圧VZは実験の結果、VZ=VT+(1/3)VBLUK
与えられると判明した。ここで、VTはSiO2膜4
の表面電荷密度QSSが2×1011atms/cm2とすると
約50vとなる。よつてVZ≒50×1000/3≒388
(v) この値は例えば通常点火装置用の出力トランジ
スタに使用する保護用ツエナーダイオードの規格
330t<VZ<VCEOを満足し、そのバラツキも実験
結果によれば、上述した反転層7により領域2,
3すなわちアノード・カソード間の距離がVZ
寄与しなくなる反転層のバツフア効果のため、±
5%程度となり、第1,2図に示す如き従来の構
造の素子バラツキの実測値±20%に比較して格段
に小さくなる。
Therefore, the operation based on the structure of the present invention will be explained.
The original withstand voltage V BLUK of the semiconductor substrate is about 1000v,
A transistor with a base and an emitter inside the substrate.
V CEO is about 400v. As a result of experiments, it was found that the breakdown voltage V Z based on the structure of the present invention is given by V Z =V T +(1/3)V BLUK . Here, V T is SiO 2 film 4
If the surface charge density Q SS is 2×10 11 atms/cm 2 , it will be about 50 V. Yotsute V Z ≒50×1000/3≒388
(v) This value is, for example, the standard for a protective Zener diode normally used in an output transistor for an ignition system.
According to the experimental results, the above-mentioned inversion layer 7 satisfies 330t < V
3. In other words, due to the buffer effect of the inversion layer where the distance between the anode and cathode no longer contributes to V Z , ±
This is about 5%, which is much smaller than the actually measured element variation of ±20% in the conventional structure as shown in FIGS.

また経時変化によるVZの安定性についても、
特に外部電荷から動作部がシールドされており、
さらに膜内部の可動電荷の影響に対しては、通常
のゲツタリングを行つた場合Naイオン等の正電
荷がほとんどで、本実施例のように基本をN型と
しゲートGをアノードAとトランジスタのベース
に共通とする構造では、ゲートGは負電位となる
ため、正電荷はゲート側に引きよせられ、動作部
である基体の表面への影響はほとんど無く非常に
安定したVZが得られる。
Also, regarding the stability of V Z due to changes over time,
In particular, the operating parts are shielded from external charges,
Furthermore, regarding the influence of mobile charges inside the film, when ordinary gettering is performed, most of the positive charges are Na ions, etc., and as in this example, the basic type is N type, and the gate G is connected to the anode A and the base of the transistor. In the structure common to both, since the gate G has a negative potential, positive charges are attracted to the gate side, and there is almost no influence on the surface of the base body, which is the operating part, and a very stable V Z can be obtained.

第9図a,bに本実施例による試作品のBT試
験(この場合逆方向電圧300v、170℃高温雰囲
気)の結果を示す。170℃という高温で測定した
経過時間に対するリーク電流Iと降伏電圧VZ
変化を示すものであるが、全く変動していない。
さらに本素子を第7図で示す等価回路でゲート電
圧を変化させてI−V特性をみたのが第8図で示
す動作特性であり、 VZ=aVG
Figures 9a and 9b show the results of a BT test (in this case, a reverse voltage of 300 V and a high temperature atmosphere of 170° C.) of a prototype according to this example. It shows changes in leakage current I and breakdown voltage V Z over time measured at a high temperature of 170° C., and they do not change at all.
Furthermore, the operating characteristics shown in Fig. 8 are obtained by changing the gate voltage and looking at the I-V characteristics of this device using the equivalent circuit shown in Fig. 7, where V Z = aV G

Claims (1)

【特許請求の範囲】 1 所定の導電型の半導体基体と、 前記半導体基体の一主表面に形成され、該基体
の導電型と反対導電型の第1領域と、 前記半導体基体の一主表面に前記第1領域と離
間して形成され、該基体と同一導電型でかつ該基
体より高不純物濃度の第2領域と、 前記第1領域及び前記第2領域間の基体表面上
の一部または全部を絶縁膜を介して覆い、かつそ
の少なくとも一部が前記第1領域及び第2領域の
一部と前記絶縁膜を介して重なり合うように配置
されたゲート電極となる導電膜と、 前記第1領域に電気接続したアノード電極と、 前記半導体基体の裏面に電気接続したカソード
電極とを備え、 前記ゲート電極と前記アノード電極との間に所
定の電位差を与えたことを特徴とする半導体装
置。
[Scope of Claims] 1. A semiconductor substrate having a predetermined conductivity type, a first region formed on one main surface of the semiconductor substrate and having a conductivity type opposite to that of the substrate, and a first region formed on one main surface of the semiconductor substrate. a second region formed apart from the first region, having the same conductivity type as the substrate and having a higher impurity concentration than the substrate; and a part or all of the surface of the substrate between the first region and the second region. a conductive film that serves as a gate electrode and is disposed such that at least a portion of the conductive film overlaps a portion of the first region and a portion of the second region with the insulating film interposed therebetween; A semiconductor device comprising: an anode electrode electrically connected to the semiconductor substrate; and a cathode electrode electrically connected to the back surface of the semiconductor substrate, and a predetermined potential difference is applied between the gate electrode and the anode electrode.
JP21564981A 1981-12-24 1981-12-24 Semiconductor device Granted JPS58111369A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP21564981A JPS58111369A (en) 1981-12-24 1981-12-24 Semiconductor device
EP82111854A EP0083060B2 (en) 1981-12-24 1982-12-21 Semiconductor device including overvoltage protection diode
DE8282111854T DE3276091D1 (en) 1981-12-24 1982-12-21 Semiconductor device including overvoltage protection diode
US07/407,157 US5596217A (en) 1981-12-24 1989-09-14 Semiconductor device including overvoltage protection diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21564981A JPS58111369A (en) 1981-12-24 1981-12-24 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS58111369A JPS58111369A (en) 1983-07-02
JPH0312458B2 true JPH0312458B2 (en) 1991-02-20

Family

ID=16675895

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21564981A Granted JPS58111369A (en) 1981-12-24 1981-12-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58111369A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160665A (en) * 1984-01-31 1985-08-22 Nec Kansai Ltd Semiconductor device
JPS61123549U (en) * 1985-01-22 1986-08-04
WO1993019490A1 (en) * 1992-03-23 1993-09-30 Rohm Co., Ltd. Voltage regulating diode

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5122379A (en) * 1974-08-19 1976-02-23 Sony Corp
JPS5556656A (en) * 1978-10-23 1980-04-25 Nec Corp Semiconductor device
JPS5580352A (en) * 1978-12-12 1980-06-17 Fuji Electric Co Ltd Transistor with high breakdown voltage

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5122379A (en) * 1974-08-19 1976-02-23 Sony Corp
JPS5556656A (en) * 1978-10-23 1980-04-25 Nec Corp Semiconductor device
JPS5580352A (en) * 1978-12-12 1980-06-17 Fuji Electric Co Ltd Transistor with high breakdown voltage

Also Published As

Publication number Publication date
JPS58111369A (en) 1983-07-02

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