JPH03119790A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03119790A JPH03119790A JP1257250A JP25725089A JPH03119790A JP H03119790 A JPH03119790 A JP H03119790A JP 1257250 A JP1257250 A JP 1257250A JP 25725089 A JP25725089 A JP 25725089A JP H03119790 A JPH03119790 A JP H03119790A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- printed circuit
- cut surface
- wiring pattern
- organic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 239000011368 organic material Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 25
- 239000000463 material Substances 0.000 abstract description 14
- 239000003365 glass fiber Substances 0.000 abstract description 7
- 239000004709 Chlorinated polyethylene Substances 0.000 abstract description 2
- 239000000470 constituent Substances 0.000 abstract description 2
- 230000035515 penetration Effects 0.000 abstract 2
- 239000002994 raw material Substances 0.000 abstract 1
- 239000003822 epoxy resin Substances 0.000 description 14
- 229920000647 polyepoxide Polymers 0.000 description 14
- 229920005989 resin Polymers 0.000 description 12
- 239000011347 resin Substances 0.000 description 12
- 238000007789 sealing Methods 0.000 description 8
- 239000004593 Epoxy Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 229920001342 Bakelite® Polymers 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 239000004637 bakelite Substances 0.000 description 4
- 239000002654 heat shrinkable material Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 101100136092 Drosophila melanogaster peng gene Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- -1 pulp Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野〉
本発明は、半導体素子等を搭載する有機性基板を用いた
半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device using an organic substrate on which a semiconductor element or the like is mounted.
（従来の技術）
従来、このような分野としては、例えば第２図のような
ものがあった。以下、その構成を図を用いて説明する。(Prior Art) Conventionally, such fields include, for example, the one shown in FIG. The configuration will be explained below using figures.
第２図は、従来の半導体装置の一構成例を示す断面図で
ある。FIG. 2 is a cross-sectional view showing an example of the configuration of a conventional semiconductor device.
この半導体装置は、例えば硝子エポキシ基板やベークラ
イト基板等の有機性基板からなる印刷配線基板（以下、
プリント基板という）１を有し、そのプリント基板１の
表面には導電性の配線パターン２が形成されている。プ
リント基板１上には半導体素子３が搭載され、それがエ
ポキシ樹脂等の接着剤４で固着されている。半導体素子
３の電極部はワイヤ５によって配線パターン２と接続さ
れている。半導体素子３の周囲の配線パターン２には、
封止枠６が載置され、それが接着剤７により配線パター
ン２に接着されている。This semiconductor device includes a printed wiring board (hereinafter referred to as
The printed circuit board 1 has a conductive wiring pattern 2 formed on its surface. A semiconductor element 3 is mounted on a printed circuit board 1, and is fixed with an adhesive 4 such as epoxy resin. The electrode portion of the semiconductor element 3 is connected to the wiring pattern 2 by a wire 5. The wiring pattern 2 around the semiconductor element 3 includes
A sealing frame 6 is placed and bonded to the wiring pattern 2 with an adhesive 7.
封止枠６にはエポキシ樹脂等からなる樹脂部材８が充填
され、その樹脂部材８によって半導体素子３とその半導
体素子３及び配線パターン２の接続箇所とが樹脂封止さ
れている。The sealing frame 6 is filled with a resin member 8 made of epoxy resin or the like, and the semiconductor element 3 and the connection portion between the semiconductor element 3 and the wiring pattern 2 are sealed with the resin member 8.
第３図（ａ＞、（ｂ）は、第１図中のプリント基板１の
内部構成例を示す断面図であり、同図（ａ）は硝子エポ
キシ基板、同図（ｂ）はベークライト基板をそれぞれ示
している。FIGS. 3(a) and 3(b) are cross-sectional views showing an example of the internal structure of the printed circuit board 1 in FIG. 1, where (a) shows a glass epoxy board and FIG. are shown respectively.
第３図（ａ）に示す硝子エポキシ基板は、硝子繊維１ａ
を織ったシート状のものに有機材料であるエポキシ樹脂
１ｂ等を染み込ませて積層した基板である。また、第３
図（ｂ）に示すベークライト基板は、パルプ１ｃをシー
ト状にしたものに、硝子エポキシ基板と同様に有機材料
であるエポキシ樹脂１ｂ等を染み込ませて積層した基板
である。The glass epoxy substrate shown in FIG. 3(a) consists of glass fibers 1a
This is a board made by laminating a sheet-like material made of woven materials impregnated with an organic material such as epoxy resin 1b. Also, the third
The Bakelite substrate shown in Figure (b) is a substrate in which a sheet of pulp 1c is impregnated with epoxy resin 1b, which is an organic material like the glass epoxy substrate, and then laminated thereon.
これら硝子繊維１ａやパルプ１ｃを基板材料の一部に用
いるにより、プリント基板１の強度を図っている。By using these glass fibers 1a and pulp 1c as part of the substrate material, the strength of the printed circuit board 1 is increased.
（発明が解決しようとする課題）
しかしながら、上記構成の半導体装置には、次のような
課題があった。(Problems to be Solved by the Invention) However, the semiconductor device having the above configuration has the following problems.
通常、同一のプリント基板１上には、半導体装置が多数
個製造される。それら半導体装置を個片にするため、機
械的にプリント基板１を切断することが行われている。Usually, a large number of semiconductor devices are manufactured on the same printed circuit board 1. In order to separate these semiconductor devices into individual pieces, the printed circuit board 1 is mechanically cut.
第４図は、第１図中のプリント基板１を切断した時の切
断面を示す図である。FIG. 4 is a diagram showing a cut surface when the printed circuit board 1 in FIG. 1 is cut.
この図が示すように、プリント基板１を切断した切断面
１ｄには、硝子繊維１ａやパルプ１ｃの残渣１ａ−１，
１ｃ−１、さらにエポキシ樹脂１ｂの残渣１ｂ−１が生
ずる。この切断後のプリント基板１に半導体素子３が搭
載され、例えば、アナログ式時計に実装された場合、こ
れら残渣１ａ−１，１ｂ−１，１ｃ−１が脱落して時計
部品の駆動部分の歯車等に挟まり、駆動部分を停止する
虞があった。As shown in this figure, on the cut surface 1d of the printed circuit board 1, there are residues 1a-1, 1a-1,
1c-1 and a residue 1b-1 of the epoxy resin 1b are produced. When the semiconductor element 3 is mounted on the printed circuit board 1 after cutting and is mounted, for example, in an analog watch, these residues 1a-1, 1b-1, 1c-1 fall off and become part of the gears of the drive part of the watch part. There was a risk that the drive part would stop if it got caught between the parts.
さらに、プリント基板１の切断面から水分等が侵入し、
基板の信頼性を低下させるという問題があった。Furthermore, moisture etc. enters from the cut surface of the printed circuit board 1,
There was a problem in that the reliability of the board was reduced.
本発明は前記従来技術が持ってした課題として、プリン
ト基板に生じた残渣が脱落するという点、および基板の
信頼性を低下させるという点について解決した半導体装
置を提供するものである。The present invention provides a semiconductor device that solves the problems of the prior art, such as the fact that residue generated on a printed circuit board falls off and the reliability of the circuit board is reduced.
（課題を解決するための手段）
本発明は、前記課題を解決するなめに、配線パターンが
形成され、所定の大きさに切断された有機性基板と、前
記有機性基板上に搭載され、前記配線パターンに接続さ
れた半導体素子とを備えた半導体装置において、次のよ
うな手段を講じたものである。(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides an organic substrate on which a wiring pattern is formed and cut into a predetermined size; In a semiconductor device including a semiconductor element connected to a wiring pattern, the following measures are taken.
前記有機性基板における切断面の一部または全部を、有
機材料で被覆したものである。A part or all of the cut surface of the organic substrate is coated with an organic material.
（作用）
本発明によれば、以上のように半導体装置を構成しなの
で、有機性基板の切断面に被覆した有機材料は、その有
機性基板の構成素材である硝子繊維、パルプ、樹脂等の
残渣の脱落を防止し、さらに水分の侵入を防止するよう
に働く。(Function) According to the present invention, since the semiconductor device is configured as described above, the organic material coated on the cut surface of the organic substrate is the constituent material of the organic substrate such as glass fiber, pulp, resin, etc. It works to prevent residue from falling off and also to prevent moisture from entering.
したがって、前記課題を解決することができるのである
。Therefore, the above problem can be solved.
（実施例）
第１図は、本発明の第１の実施例を示す半導体装置の縦
断面図である。(Embodiment) FIG. 1 is a longitudinal sectional view of a semiconductor device showing a first embodiment of the present invention.
この半導体装置は、チップ・オン・ボード（Ｃｈｉｐ
ｏｎ Ｂｏａｒｄ）と称されるタイプのものである
。例えば硝子エポキシ基板やベークライト基板等の有機
性基板からなる絶縁性のプリント基板２０を宥し、その
プリント基板２ｏの表面には銅箔等からなる導電性の配
線パターン２１が形成されている。This semiconductor device is a chip-on-board (Chip-on-board)
This is a type called "on Board". For example, an insulating printed circuit board 20 made of an organic substrate such as a glass epoxy board or a Bakelite board is prepared, and a conductive wiring pattern 21 made of copper foil or the like is formed on the surface of the printed board 2o.
プリント基板２０上には半導体素子２２が搭載され、そ
れが導電性エポキシ樹脂等の接着剤２３や金（Ａｕ）−
シリコン（Ｓｉ）共晶合金法等によって固着されている
。半導体素子２２の電極部はアルミニューム（Ａｕ）、
金（Ａｕ）等のワイヤ２４によって配線パターン２１の
接続部と接続されている。半導体素子２２の周囲の配線
パターン２１には、封止枠２５が載置され、その封止枠
２５がエポキシ樹脂等の接着剤２６により配線パターン
２１に接着されている。封止枠２５は、例えば紙、また
は布にエポキシ樹脂、フェノール樹脂等を含浸させて個
化した後、プレス等により打ち抜いて製造される。A semiconductor element 22 is mounted on a printed circuit board 20, and is coated with an adhesive 23 such as conductive epoxy resin or gold (Au).
It is fixed by a silicon (Si) eutectic alloy method or the like. The electrode portion of the semiconductor element 22 is made of aluminum (Au),
It is connected to the connecting portion of the wiring pattern 21 by a wire 24 made of gold (Au) or the like. A sealing frame 25 is placed on the wiring pattern 21 around the semiconductor element 22, and the sealing frame 25 is adhered to the wiring pattern 21 with an adhesive 26 such as epoxy resin. The sealing frame 25 is manufactured by, for example, impregnating paper or cloth with epoxy resin, phenol resin, etc., individualizing it, and then punching it out using a press or the like.
封止枠２５内にはエポキシ、シリコン、ポリイミド樹脂
等からなる樹脂部材２７が充填され、その樹脂部材２７
によって半導体素子２２、ワイヤ２４、及びワイヤ２４
と配線パターン２１の接続箇所とが樹脂封止されている
。The sealing frame 25 is filled with a resin member 27 made of epoxy, silicone, polyimide resin, etc.
The semiconductor element 22, the wire 24, and the wire 24
and the connection portion of the wiring pattern 21 are sealed with resin.
さらに、プリント基板２０の周囲に、塩素化ポリエチレ
ン等の有機材料である熱収縮材（旭電気工業（株）アゾ
カブレインＣＥ等）をセットして後、加熱することで、
プリント基板２０の切断面２０ａである側面全体にその
熱収縮材２８が貼設されている。Furthermore, by setting a heat-shrinkable material (such as Azocabrain CE, manufactured by Asahi Electric Industry Co., Ltd.), which is an organic material such as chlorinated polyethylene, around the printed circuit board 20, and then heating it,
The heat shrink material 28 is attached to the entire side surface of the printed circuit board 20, which is the cut surface 20a.
第５図は、第１図の斜視図である。FIG. 5 is a perspective view of FIG. 1.
プリント基板２０上には、配線パターン２１および素子
搭載部２９が形成されている。この素子搭載部２つには
、第１図に示した半導体素子２２、ワイヤ２４、封止枠
２５、樹脂部材２７、及び配線パターン２１の一部が内
設されている。そして、配線パターン２１の外部接続部
２１ｂによって外部端子が形成されている。さらに、プ
リント基板２０の周囲の側面全体には熱収縮材２８が貼
設されている。A wiring pattern 21 and an element mounting section 29 are formed on the printed circuit board 20. The semiconductor element 22, wire 24, sealing frame 25, resin member 27, and part of the wiring pattern 21 shown in FIG. 1 are installed inside the two element mounting parts. The external connection portion 21b of the wiring pattern 21 forms an external terminal. Further, a heat shrink material 28 is attached to the entire side surface around the printed circuit board 20.
第６図（ａ）〜（ｇ＞は、第１図中のプリント基板２０
および配線パターン２１の製造工程図である。Figures 6(a) to (g>) show the printed circuit board 20 in Figure 1.
and a manufacturing process diagram of the wiring pattern 21.
第６図（ａ）〜（ｄ）が示すように、プリント基板２０
に対して穴開は加工後、スルーホール２０ｂ内に無電解
銅メツキにより、銅の薄膜を形成し、その後、全面を電
気銅メツキにより、穴内壁が銅メツキの厚さになるよう
にメツキ付けする。As shown in FIGS. 6(a) to 6(d), the printed circuit board 20
In contrast, after drilling, a thin copper film is formed in the through hole 20b by electroless copper plating, and then the entire surface is plated with electrolytic copper plating so that the inner wall of the hole has the same thickness as the copper plating. do.
メツキ付は後、レジストメツキ、有機レジストにより回
路形成し、それ以外の不用の銅をエツチングにより除去
することでプリント基板２０上に複数の配線パターン２
１が形成される。After plating, a circuit is formed using resist plating and an organic resist, and other unnecessary copper is removed by etching to form a plurality of wiring patterns 2 on the printed circuit board 20.
1 is formed.
つづいて、第６図（ｅ）〜（ｆ）が示すように、各配線
パターン２１毎に、上金型２０ｃと下金型２０ｄとを用
いた外形抜きにより、または第６図（ｇ）が示すように
、ドリル２１ｅを用いるルータ加工と称する外形加工に
より、個片されたプリント基板２０が形成される。Next, as shown in FIGS. 6(e) to 6(f), each wiring pattern 21 is cut out using the upper mold 20c and the lower mold 20d, or as shown in FIG. 6(g). As shown, individual printed circuit boards 20 are formed by external processing called router processing using a drill 21e.
このように、配線パターン２１が形成されたプリント基
板２０上に半導体素子２２を搭載し、その半導体素子２
２とワイヤ２４を介して配線パターン２１とを接続する
等の処置を施せば、第１図の半導体装置が得られる。In this way, the semiconductor element 22 is mounted on the printed board 20 on which the wiring pattern 21 is formed, and the semiconductor element 22 is mounted on the printed circuit board 20 on which the wiring pattern 21 is formed.
2 and the wiring pattern 21 via the wire 24, the semiconductor device shown in FIG. 1 can be obtained.
この様に構成される半導体装置の動作は、配線パターン
２１の外部接続端子２１ｂから電流が入力されると、配
線パターン２１、およびワイヤ２４を介して半導体素子
２２に達する。その電流は、この半導体素子２２におい
て、所定の処理が施されて外部接続端子２１ｂの他の部
分から出力される。The operation of the semiconductor device configured in this manner is such that when a current is input from the external connection terminal 21b of the wiring pattern 21, it reaches the semiconductor element 22 via the wiring pattern 21 and the wire 24. The current is subjected to a predetermined process in this semiconductor element 22 and outputted from other parts of the external connection terminal 21b.
本実施例では、次のような利点を有している。This embodiment has the following advantages.
（イ）プリント基板２０の周囲に、熱収縮材２８をセッ
トし、その後に加熱するだけで、極めて容易にプリント
基板２０の切断面全体に熱収縮材２８が貼設できる。こ
れにより、作業性が向上する。(a) The heat shrink material 28 can be attached to the entire cut surface of the printed circuit board 20 very easily by simply setting the heat shrink material 28 around the printed circuit board 20 and then heating it. This improves work efficiency.
（口〉プリント基板２０の切断面２０ａを熱収縮材２８
で被覆したので、プリント基板２０からの残渣の脱落を
防止することができ、この半導体装置を実装した電気製
品に対してその残渣による不具合の発生を防ぐことがで
きる。(Opening) Cut the cut surface 20a of the printed circuit board 20 with heat shrink material 28
Since the printed circuit board 20 is coated with the semiconductor device, it is possible to prevent the residue from falling off the printed circuit board 20, and it is possible to prevent the occurrence of problems due to the residue in electrical products on which this semiconductor device is mounted.
（ハ）プリン）へ基板２０の切断面２０ａの全部を熱収
縮材２８で被覆したので、プリント基板２０に水分等が
侵入するのを防止でき、基板の信頼性を向上させること
ができる。(c) Since the entire cut surface 20a of the substrate 20 is covered with the heat shrink material 28, it is possible to prevent moisture and the like from entering the printed circuit board 20, thereby improving the reliability of the circuit board.
第７図は、本発明の第２の実施例を示す半導体装置の縦
断面図であり、第１図と共通の要素には同一の符号が付
されている。FIG. 7 is a longitudinal cross-sectional view of a semiconductor device showing a second embodiment of the present invention, and elements common to those in FIG. 1 are given the same reference numerals.
この半導体装置は、第１図の熱収縮材２８に代えて、塗
布可能な有機材料、例えばエポキシ系の樹脂膜２８ａで
被覆した構成であり、第１の実施例と同様の動作を行う
。This semiconductor device has a structure in which it is covered with a coatable organic material, for example, an epoxy resin film 28a, instead of the heat shrinkable material 28 in FIG. 1, and operates in the same manner as in the first embodiment.
第８図（ａ）、 （ｂ）は、第７図のプリント基板２
０の内部構成例を示す断面図であり、同図（ａ）は硝子
エポキシ基板、同図（ｂ）はベークライト基板をそれぞ
れ示している。8(a) and 8(b) show the printed circuit board 2 of FIG.
FIG. 2 is a cross-sectional view showing an example of the internal configuration of 0, in which (a) shows a glass epoxy substrate, and (b) shows a bakelite substrate.
第８図（ａ）に示すように、硝子エポキシ基板の切断面
２０ａには、硝子繊維２０ｂやエポキシ樹脂２０ｃの残
渣の脱落を防止するため、樹脂膜２８ａが塗布されてい
る。As shown in FIG. 8(a), a resin film 28a is applied to the cut surface 20a of the glass epoxy substrate in order to prevent the residues of the glass fibers 20b and epoxy resin 20c from falling off.
また、第８図（ｂ）に示すように、ベークライト基板に
は、パルプ２０ｄやエポキシ樹脂２０ｃの残渣の脱落を
防止するため、同様に、樹脂膜２８ａが形成されている
。Further, as shown in FIG. 8(b), a resin film 28a is similarly formed on the Bakelite substrate in order to prevent the residues of the pulp 20d and epoxy resin 20c from falling off.
本実施例は、次のような利点を有している。This embodiment has the following advantages.
樹脂ｙＡ２８ａは塗布時は流動性のあるので、熱収縮材
に比べ、プリント基板２０の開孔部断面に容易に用いる
ことができる。しかも、樹脂ＷＡ２８ａにエポキシ系を
使用したので、接着度が向上する。Since the resin yA28a has fluidity when applied, it can be used more easily for the cross section of the opening of the printed circuit board 20 than a heat shrinkable material. Furthermore, since an epoxy resin is used for the resin WA28a, the degree of adhesion is improved.
なお、本発明は図示の実施例に限定されず、種々の変形
が可能である。例えば、その変形例としては次のような
ものがある。Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, the following variations are available.
（Ｉ＞第１および第２の実施例では、プリント基板２０
における切断面の全部に有機材料を被覆したが、切断面
の全部に被覆する必要がない場合、または全部に被覆す
ることが不可能な場合等、必要に応じて切断面の一部だ
けに被覆してもよい（例えば、第５図に示す切断面２８
の前部や後部等）。(I>In the first and second embodiments, the printed circuit board 20
Although the entire cut surface was coated with the organic material, if it is not necessary to coat the entire cut surface or it is impossible to coat the entire cut surface, it may be necessary to coat only a part of the cut surface. (For example, the cut surface 28 shown in FIG.
front, rear, etc.).
（ＩＩ）第２の実施例では、有機材料してエポキシ系の
樹脂を用いたが、塗布可能であれば他の有機樹脂でもよ
い。(II) In the second embodiment, an epoxy resin was used as the organic material, but other organic resins may be used as long as they can be coated.
（ＩＩＩ）封止枠２５は、エポキシ樹脂等を用いてシル
ク印刷方式等によってプリント基板２０上に形成しても
よい。(III) The sealing frame 25 may be formed on the printed circuit board 20 using an epoxy resin or the like using a silk printing method or the like.
（ＩＶ）半導体基板２０上に形成された配線パターン２
１、半導体素子２２等の材質および形状等は図示のもの
に限定されない。本発明の要旨に沿ったものであれば、
いかなる変形も可能である。(IV) Wiring pattern 2 formed on semiconductor substrate 20
1. The material, shape, etc. of the semiconductor element 22 and the like are not limited to those shown in the drawings. If it is in accordance with the gist of the present invention,
Any variations are possible.
（発明の効果）
以上詳細に説明したように、本発明によれば、有機性基
板における切断面の一部または全部を、有機材料で被覆
したので、有機性基板の切断面に生じた硝子繊維、パル
プ等の残渣の脱落を防止できる。(Effects of the Invention) As explained in detail above, according to the present invention, a part or all of the cut surface of the organic substrate is coated with an organic material, so that glass fibers generated on the cut surface of the organic substrate are coated with the organic material. , it is possible to prevent residues such as pulp from falling off.
これにより、従来のように、前記残渣が脱落して、電気
製品等の、例えば駆動部分にその残渣が挟まり、製品の
使用ができなくなるといっな不都合を解消できる。This eliminates the conventional problem of the residue falling off and getting caught in, for example, a driving part of an electrical product, making the product unusable.
さらに、有機性基板の切断面の全部を有機材料で被覆す
れば、有機性基板に水分等が侵入するのを防止でき、基
板の信頼性を向上させることができる。Furthermore, if the entire cut surface of the organic substrate is coated with an organic material, it is possible to prevent moisture and the like from entering the organic substrate, thereby improving the reliability of the substrate.
第１図は本発明の第１の実施例を示す半導体装置の断面
図、第２図は従来の半導体装置の断面図、第３図＋＋＜
ａ＞、（ｂ）は第１図中のプリント基板の断面図、第４
図は第１図中のプリント基板の切断面を示す図、第５図
は第１図の斜視図、第６図（ａ）〜（ｇ）は第１図中の
プリント基板および配線パターンの製造工程図、第７図
は本発明の第２の実施例を示す半導体装置の断面図、第
８図（ａ）、（ｂ）は第７図のプリン小基板の断面図で
ある。
２０・・・・・・プリント基板、２０ａ・・・・・・切
断面、２１・・・・・・配線パターン、２２・・・・・
・半導体素子、２８・・・・・・熱収縮性材、２８ａ・
・・・・・樹脂膜。
鵬３図FIG. 1 is a sectional view of a semiconductor device showing a first embodiment of the present invention, FIG. 2 is a sectional view of a conventional semiconductor device, and FIG. 3 is a sectional view of a conventional semiconductor device.
a>, (b) are cross-sectional views of the printed circuit board in Figure 1, and Figure 4.
The figure shows a cut section of the printed circuit board in FIG. 1, FIG. 5 is a perspective view of FIG. 1, and FIGS. 6 (a) to (g) show the manufacture of the printed circuit board and wiring pattern in FIG. FIG. 7 is a sectional view of a semiconductor device showing a second embodiment of the present invention, and FIGS. 8(a) and 8(b) are sectional views of the small printed circuit board shown in FIG. 7. 20...Printed circuit board, 20a...cut surface, 21...wiring pattern, 22...
・Semiconductor element, 28... Heat shrinkable material, 28a・
...Resin film. Peng 3 figures
Claims (1)
有機性基板と、 前記有機性基板上に搭載され、前記配線パターンに接続
された半導体素子とを、備えた半導体装置において、 前記有機性基板における切断面の一部または全部を、有
機材料で被覆したことを特徴とする半導体装置。[Claims] A semiconductor device comprising: an organic substrate on which a wiring pattern is formed and cut into a predetermined size; and a semiconductor element mounted on the organic substrate and connected to the wiring pattern. A semiconductor device, wherein a part or all of the cut surface of the organic substrate is coated with an organic material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1257250A JPH03119790A (en) | 1989-10-02 | 1989-10-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1257250A JPH03119790A (en) | 1989-10-02 | 1989-10-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03119790A true JPH03119790A (en) | 1991-05-22 |
Family
ID=17303778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1257250A Pending JPH03119790A (en) | 1989-10-02 | 1989-10-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03119790A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013045962A (en) * | 2011-08-25 | 2013-03-04 | Toshiba Corp | Printed board |
| JP2014022483A (en) * | 2012-07-17 | 2014-02-03 | Ngk Spark Plug Co Ltd | Relay board and method for manufacturing the same |
-
1989
- 1989-10-02 JP JP1257250A patent/JPH03119790A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013045962A (en) * | 2011-08-25 | 2013-03-04 | Toshiba Corp | Printed board |
| JP2014022483A (en) * | 2012-07-17 | 2014-02-03 | Ngk Spark Plug Co Ltd | Relay board and method for manufacturing the same |
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