JPH0555401A - Printed wiring board - Google Patents

Printed wiring board

Info

Publication number
JPH0555401A
JPH0555401A JP3074134A JP7413491A JPH0555401A JP H0555401 A JPH0555401 A JP H0555401A JP 3074134 A JP3074134 A JP 3074134A JP 7413491 A JP7413491 A JP 7413491A JP H0555401 A JPH0555401 A JP H0555401A
Authority
JP
Japan
Prior art keywords
recess
plating layer
hole
printed wiring
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3074134A
Other languages
Japanese (ja)
Other versions
JPH0563941B2 (en
Inventor
Hiromi Ogawa
弘海 小川
Osamu Fujikawa
治 藤川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP57178663A external-priority patent/JPS5967686A/en
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP3074134A priority Critical patent/JPH0555401A/en
Publication of JPH0555401A publication Critical patent/JPH0555401A/en
Publication of JPH0563941B2 publication Critical patent/JPH0563941B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Abstract

PURPOSE:To provide a printed wiring board which has excellent humidity-proof characteristic and heat radiating characteristic and also facilitates wire bonding process and die bonding process. CONSTITUTION:In a printed wiring board having a recess 91 for mounting electronic components and a through hole 92 on an organic resin substrate 90, the recess 91 and through hole 92 have a through hole plating layer 1 and the recess 91 has vertical wall surface formed by the counterboring process. Moreover, the outer most surface of the recess 91 is covered with gold plating layer 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は,耐湿性に優れたプリン
ト配線基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board having excellent moisture resistance.

【0002】[0002]

【従来技術】電子部品の高密度実装化に伴って,半導体
素子等の電子部品を,ザグリ加工により形成した凹部内
に搭載する方法が行われている。この方法は,例えば時
計などの薄型部品に用いるプリント配線基板に対して採
用されている。また,プリント配線基板においては,導
体回路を形成するための絶縁基板として,軽量かつ加工
容易性等の点から有機系樹脂基板を用いることが多い。
該有機系樹脂基板としては,例えば紙フェノール銅張積
層基板,或いはガラスエポキシ銅張積層基板等が用いら
れる。
2. Description of the Related Art Along with the high density mounting of electronic parts, a method of mounting electronic parts such as semiconductor elements in recesses formed by counterboring has been performed. This method is adopted for printed wiring boards used for thin parts such as watches. In a printed wiring board, an organic resin board is often used as an insulating board for forming a conductor circuit because of its light weight and ease of processing.
As the organic resin substrate, for example, a paper phenol copper clad laminated substrate, a glass epoxy copper clad laminated substrate, or the like is used.

【0003】[0003]

【解決しようとする課題】しかしながら,上記有機系樹
脂基板は吸湿性が大きく,これに搭載した電子部品に湿
気が浸入し,その電子機能に障害を与えるおそれが多
い。特に,上記のごとく,凹部内に電子部品を搭載した
場合には,ザグリ加工した凹部の壁面から電子部品内に
湿気が浸入し易い。即ち,図12に示すごとく,プリン
ト配線基板9の有機系樹脂基板90に,ザグリ加工によ
り凹部91を設けた場合,ザグリ加工によって切削形成
された壁面910,底面911には,有機系樹脂基板の
芯である紙繊維やガラス繊維などの多数の繊維93が,
長さ約5μm程度のヒゲ状に露出する。このことは,有
機系樹脂基板90に穿設したスルーホール92の壁面9
20においても同様である。なお,該スルーホール92
は,導体ピンを挿入する孔である。
However, the above organic resin substrate has a high hygroscopic property, so that moisture may infiltrate into electronic components mounted on the organic resin substrate, which often impairs its electronic function. Especially, as described above, when an electronic component is mounted in the recess, moisture easily enters the electronic component from the wall surface of the recessed recess. That is, as shown in FIG. 12, when the concave portion 91 is provided in the organic resin substrate 90 of the printed wiring board 9 by the counterbore processing, the wall surface 910 and the bottom surface 911 formed by the counterbore processing have the organic resin substrate Many fibers 93 such as paper fibers and glass fibers which are cores,
It is exposed as a beard with a length of about 5 μm. This means that the wall surface 9 of the through hole 92 formed in the organic resin substrate 90 is
The same applies to 20. The through hole 92
Is a hole for inserting a conductor pin.

【0004】そして,上記のごとく露出した繊維93
は,凹部壁面においては,上記フェノール樹脂等の樹脂
との境界面に小さい環状の間隙を有している。そして,
この境界間隙は上記繊維93の周囲に沿って,有機系樹
脂基板90の内部を経てその外部,つまりプリント配線
基板9の外部へ通じている。そのため,この境界間隙を
通じて,プリント配線基板9の外部から,上記凹部91
内へ湿気が浸入してくることになる。それ故,かかる湿
気浸入に対する,耐湿性の向上が望まれる。また,プリ
ント配線基板9に搭載した電子部品から発せられる熱
は,出来る限り速く外部へ放出させる必要がある。特
に,上記のごとく凹部91内に電子部品を搭載した場合
には,電子部品はその周囲が伝熱性の低い有機系樹脂の
壁面によって囲まれているため,熱放散が円滑でない。
The exposed fiber 93 as described above
Has a small annular gap at the interface with the resin such as the phenol resin on the wall surface of the recess. And
This boundary gap extends along the periphery of the fiber 93, through the inside of the organic resin substrate 90 to the outside thereof, that is, the outside of the printed wiring board 9. Therefore, from the outside of the printed wiring board 9 through the boundary gap, the recess 91
Moisture will enter the inside. Therefore, improvement in moisture resistance against such infiltration of moisture is desired. Further, the heat generated from the electronic components mounted on the printed wiring board 9 must be released to the outside as quickly as possible. In particular, when the electronic component is mounted in the recess 91 as described above, the heat dissipation is not smooth because the periphery of the electronic component is surrounded by the wall surface of the organic resin having low heat conductivity.

【0005】一方,上記熱放散を促進させるため,凹部
の壁面を,上方へ拡開する傾斜面とすることも考えられ
る(例えば特開昭52−47692号公報参照)。しか
し,かかる方法によるときには,基板上の導体回路と電
子部品との間に接続するボンディングの距離が長くな
り,ボンディング操作が困難となる。また,ボンディン
グワイヤーが長くなるため,多数のボンディングワイヤ
ーが互いに接触するおそれを生じ,またボンディングワ
イヤーのコストが高くなる。本発明はかかる従来の問題
点に鑑み,耐湿性及び放熱性に優れたプリント配線基板
を提供しようとするものである。
On the other hand, in order to promote the heat dissipation, it may be considered that the wall surface of the recess is an inclined surface that expands upward (for example, see Japanese Patent Laid-Open No. 52-47692). However, according to such a method, the bonding distance between the conductor circuit on the substrate and the electronic component becomes long, and the bonding operation becomes difficult. Further, since the bonding wire becomes long, there is a risk that a large number of bonding wires will come into contact with each other, and the cost of the bonding wire will increase. In view of such conventional problems, the present invention intends to provide a printed wiring board excellent in moisture resistance and heat dissipation.

【0006】[0006]

【課題の解決手段】本発明は,有機系樹脂基板に電子部
品搭載用の凹部とスルーホールとを設けてなるプリント
配線基板において,上記凹部はザグリ加工により形成さ
れた垂直壁面を有すると共に該凹部の底面と垂直壁面の
全表面及びスルーホールはスルーホールメッキ層を有
し,また凹部のスルーホールメッキ層の表面は金メッキ
層により被覆されており,上記スルーホールメッキ層及
び金メッキ層が,有機系樹脂基板の内部に浸入した湿気
が上記凹部内に浸入することを阻止していることを特徴
とするプリント配線基板にある。
According to the present invention, there is provided a printed wiring board comprising an organic resin substrate provided with a recess for mounting electronic parts and a through hole, the recess having a vertical wall surface formed by counterboring, and the recess. The bottom surface and the entire surface of the vertical wall surface and the through hole have a through hole plating layer, and the surface of the through hole plating layer of the recess is covered with a gold plating layer. The printed wiring board is characterized in that moisture that has entered the inside of the resin substrate is prevented from entering the recesses.

【0007】本発明において,上記スルーホールメッキ
層とは,上記スルーホールの内壁に被覆する金属メッキ
層のことをいう。本発明においては,このスルーホール
メッキ層と同じ金属メッキ層を,上記凹部に被覆してい
る。それ故,本発明では,スルーホール内及び凹部内に
設ける上記金属メッキ層は,これを総称して「スルーホ
ールメッキ層」としているのである。また,それ故に,
該スルーホールメッキ層は凹部内,スルーホール内とも
にほぼ同じ厚みに形成されている。そして,上記スルー
ホールメッキ層の厚みは,プリント配線基板に関して世
界的に標準規格として採用されている「IPC STA
NDARD」(1981年発行,IPC−D−320
A,第2〜第3頁の3.5.2.3項及び第5表)にも
紹介されているように,通常10〜50μm程度の比較
的大きい厚みを有している。また,上記スルーホールメ
ッキ層としては,例えば銅メッキ層を用いる。
In the present invention, the through hole plating layer means a metal plating layer covering the inner wall of the through hole. In the present invention, the recess is coated with the same metal plating layer as the through hole plating layer. Therefore, in the present invention, the metal plating layers provided in the through holes and the recesses are collectively referred to as "through hole plating layers". Also, therefore,
The through hole plating layer is formed to have substantially the same thickness in the recess and the through hole. The thickness of the through-hole plating layer is "IPC STA" which is adopted as a standard worldwide for printed wiring boards.
NDARD "(issued in 1981, IPC-D-320
It has a relatively large thickness of usually about 10 to 50 μm, as also introduced in A., 3.5.2.3 on page 2-3 and Table 5). As the through hole plating layer, for example, a copper plating layer is used.

【0008】また,上記凹部は,ザグリ加工によって形
成された垂直壁面を有する。また,該凹部の最表面に
は,電子部品の搭載を容易にするための金メッキ層が被
覆されている。次に,上記プリント配線基板を製造する
方法としては,例えば,有機系樹脂基板に,スルーホー
ルを形成すると共にザグリ加工により電子部品搭載用の
垂直壁面を有する凹部を形成し,次いで該スルーホール
及び凹部の表面に同時にスルーホールメッキ層を被覆
し,次いで所望の導体回路を形成し,その後上記凹部の
最表面に金メッキ層を被覆することを特徴とするプリン
ト配線基板の製造方法がある。
The recess has a vertical wall surface formed by counterboring. The outermost surface of the recess is covered with a gold plating layer for facilitating mounting of electronic components. Next, as a method for manufacturing the above-mentioned printed wiring board, for example, a through hole is formed in an organic resin substrate and a recess having a vertical wall surface for mounting an electronic component is formed by counterboring, and then the through hole and the through hole are formed. There is a method of manufacturing a printed wiring board characterized in that the surface of the recess is coated with a through-hole plating layer at the same time, then a desired conductor circuit is formed, and then the outermost surface of the recess is coated with a gold plating layer.

【0009】[0009]

【作用及び効果】本発明にかかるプリント配線基板にお
いては,電子部品搭載用の凹部は,スルーホール内と同
様にスルーホールメッキ層が形成されている。そして,
該スルーホールメッキ層は前記のごとく比較的大きい厚
みを有している。そのため,凹部の壁面は,全てこの厚
いスルーホールメッキ層によって被覆される。それ故,
有機系樹脂基板の内部を通じて上記凹部内に湿気が浸入
してくることは絶対にない。
In the printed wiring board according to the present invention, the through hole plating layer is formed in the recess for mounting the electronic component as in the through hole. And
The through-hole plating layer has a relatively large thickness as described above. Therefore, the wall surface of the recess is entirely covered with this thick through-hole plating layer. Therefore,
Moisture never enters the recesses through the organic resin substrate.

【0010】即ち,前記従来技術の項で図12に示した
ごとく,ザグリ加工した凹部91の壁面910,底面9
11には,ガラス繊維等の繊維93が長さ5μm程度の
ヒゲ状に多数露出している。しかし,本発明では,後述
する図1に示すごとく,凹部91内の垂直壁面915
は,上記のごとく比較的大きい厚みの上記スルーホール
メッキ層1によって被覆されている。そのため,上記ヒ
ゲ状の繊維93は,上記スルーホールメッキ層1の中へ
埋没した状態となる。このことは凹部の底面についても
同じである(以下同様)。それ故,従来のごとく,上記
繊維93と有機系樹脂基板の樹脂との間の境界間隙は,
スルーホールメッキ層1により閉塞されることになる。
したがって,凹部91内への湿気浸入がない。なお,図
1において,符号2は,凹部最表面に被覆した金メッキ
層である。
That is, as shown in FIG. 12 in the section of the prior art, the wall surface 910 and the bottom surface 9 of the recessed portion 91 which has been countersunk are processed.
A large number of fibers 93 such as glass fibers are exposed at 11 in the form of a mustache having a length of about 5 μm. However, in the present invention, as shown in FIG.
Are covered with the through-hole plating layer 1 having a relatively large thickness as described above. Therefore, the beard-shaped fibers 93 are buried in the through-hole plating layer 1. The same applies to the bottom surface of the recess (and so on). Therefore, as in the conventional case, the boundary gap between the fiber 93 and the resin of the organic resin substrate is
It will be blocked by the through-hole plating layer 1.
Therefore, there is no infiltration of moisture into the recess 91. In FIG. 1, reference numeral 2 is a gold plating layer that covers the outermost surface of the recess.

【0011】また,本発明における凹部の壁面は,垂直
壁面であり,外方へ拡開していない。それ故,該凹部内
に搭載した電子部品と,該凹部の開口周縁に位置する導
体回路との間は,最短距離とすることができる。そのた
め,電子部品と導体回路間に接続するボンディングワイ
ヤーの長さを短くでき,またボンディング操作が容易で
ある。また,凹部は,垂直壁面を有し,電子部品と垂直
壁面との間は最短距離が形成される。そのため,電子部
品で発生した熱は,その側面より容易に垂直壁面に伝わ
り,該垂直壁面に設けた金メッキ層,スルーホールメッ
キ層を経て容易に外部へ放散される。それ故,電子部品
の放熱性促進にも優れている。
Further, the wall surface of the recess in the present invention is a vertical wall surface and does not spread outward. Therefore, the shortest distance can be provided between the electronic component mounted in the recess and the conductor circuit located at the peripheral edge of the opening of the recess. Therefore, the length of the bonding wire connected between the electronic component and the conductor circuit can be shortened, and the bonding operation is easy. Further, the recess has a vertical wall surface, and the shortest distance is formed between the electronic component and the vertical wall surface. Therefore, the heat generated in the electronic component is easily transmitted from the side surface to the vertical wall surface and easily dissipated to the outside through the gold plating layer and the through hole plating layer provided on the vertical wall surface. Therefore, it is also excellent in promoting heat dissipation of electronic parts.

【0012】更に,凹部の最表面には上記金メッキ層が
設けられているので,共晶合金(金−錫ロウ材)を用い
て電子部品を接合する場合には,そのダイボンディング
が容易となる。上記のごとく,本発明によれば,耐湿
性,放熱性に優れ,更にはワイヤーボンディング操作及
び共晶合金によるダイボンディングも容易なプリント配
線基板を提供することができる。
Furthermore, since the gold plating layer is provided on the outermost surface of the recess, die bonding can be facilitated when electronic components are joined using a eutectic alloy (gold-tin brazing material). .. As described above, according to the present invention, it is possible to provide a printed wiring board which is excellent in moisture resistance and heat dissipation and is easy to perform wire bonding operation and die bonding with a eutectic alloy.

【0013】[0013]

【実施例】実施例1 本発明の実施例にかかるプリント配線基板につき,図1
及び図2を用いて説明する。本例のプリント配線基板1
0は,図1に示すごとく,有機系樹脂基板90に電子部
品搭載の凹部91とスルーホール92とを設けてなる。
そして,上記凹部91及びスルーホール92の全表面に
はスルーホールメッキ層1がそれぞれ形成されている。
また,上記凹部91はザグリ加工により作られた垂直壁
面915を有する。そして,該凹部91の最表面には,
金メッキ層2を形成している。また,図1において符号
96は導体回路である。
EXAMPLE Example 1 A printed wiring board according to an example of the present invention is shown in FIG.
2 and FIG. 2. Printed wiring board 1 of this example
0, as shown in FIG. 1, is an organic resin substrate 90 provided with a recess 91 for mounting electronic components and a through hole 92.
The through hole plating layer 1 is formed on the entire surfaces of the recess 91 and the through hole 92.
Further, the recess 91 has a vertical wall surface 915 formed by counterboring. Then, on the outermost surface of the recess 91,
The gold plating layer 2 is formed. Further, in FIG. 1, reference numeral 96 is a conductor circuit.

【0014】次に,上記のごとく構成されたプリント配
線基板には,図2に示すごとく,その凹部91内に,半
導体素子等の電子部品5を搭載する。該電子部品5は,
その下面が凹部91の底面の金メッキ層2に対して,共
晶合金(Au−Snロウ)により接合(ダイボンディン
グ)されている。また,上記電子部品5と,プリント配
線基板上の導体回路96との間には,ボンディングワイ
ヤー51が接続されている。更に,電子部品5の周囲
は,ボンディングワイヤー51を含めて,エポキシ樹脂
等の封止樹脂55により覆われている。上記のごとく,
本例のプリント配線基板1においては,凹部91の垂直
壁面915及び底面が,スルーホール92の壁面と同様
にスルーホールメッキ層1により被覆されている。そし
て,該スルーホールメッキ層1は,通常10〜50μm
程度の厚みに形成されている。
Next, as shown in FIG. 2, the electronic component 5 such as a semiconductor element is mounted in the recess 91 of the printed wiring board constructed as described above. The electronic component 5 is
The lower surface is joined (die-bonded) to the gold plating layer 2 on the bottom surface of the recess 91 by a eutectic alloy (Au—Sn solder). A bonding wire 51 is connected between the electronic component 5 and the conductor circuit 96 on the printed wiring board. Further, the periphery of the electronic component 5, including the bonding wire 51, is covered with a sealing resin 55 such as epoxy resin. As mentioned above,
In the printed wiring board 1 of this example, the vertical wall surface 915 and the bottom surface of the recess 91 are covered with the through-hole plating layer 1 similarly to the wall surface of the through hole 92. The through-hole plating layer 1 usually has a thickness of 10 to 50 μm.
It is formed with a certain thickness.

【0015】そのため,凹部のザグリ加工時において,
その垂直壁面915,底面911に露出したヒゲ状(長
さ5μm程度)の繊維93(前記図12参照)は,図1
に示すごとくスルーホールメッキ層1の中に埋没された
状態となる。それ故,基板の外部から繊維93に沿っ
て,有機系樹脂基板90の内部を経由して,凹部91内
に湿気が浸入してくることは,絶対にない。また,上記
凹部91の側壁は,垂直壁面であり,外方へ拡開してい
ない。そのため,該凹部91内に搭載した電子部品5と
導体回路96との間は最短距離となる。それ故,両者間
を結ぶボンディングワイヤーの長さは最短となり,コス
トも安く,またボンディング操作も容易である。
Therefore, at the time of counter boring the recess,
The beard-shaped (about 5 μm long) fibers 93 (see FIG. 12) exposed on the vertical wall surface 915 and the bottom surface 911 are shown in FIG.
As shown in FIG. 5, the through hole plating layer 1 is buried. Therefore, moisture never enters the concave portion 91 from the outside of the substrate along the fiber 93 via the inside of the organic resin substrate 90. Further, the side wall of the recess 91 is a vertical wall surface and does not expand outward. Therefore, the distance between the electronic component 5 mounted in the recess 91 and the conductor circuit 96 is the shortest. Therefore, the length of the bonding wire connecting the two becomes the shortest, the cost is low, and the bonding operation is easy.

【0016】また,凹部91は垂直壁面915を有する
ため,該垂直壁面915と電子部品5との間は最短距離
が形成される。そのため,プリント配線基板5で発生し
た熱は,その側面より垂直壁面915に容易に伝わり,
金メッキ層2,スルーホールメッキ層1を経て容易に外
部へ放散される。それ故,電子部品の放熱性にも優れて
いる。更に,凹部91の表面には金メッキ層2が被覆し
てあるので,上記のごとく共晶合金を用いたダイボンデ
ィングも,容易に行うことができる。
Further, since the concave portion 91 has the vertical wall surface 915, the shortest distance is formed between the vertical wall surface 915 and the electronic component 5. Therefore, the heat generated in the printed wiring board 5 is easily transferred from the side surface to the vertical wall surface 915,
It is easily diffused to the outside through the gold plating layer 2 and the through hole plating layer 1. Therefore, the heat dissipation of electronic parts is also excellent. Further, since the surface of the recess 91 is covered with the gold plating layer 2, die bonding using the eutectic alloy can be easily performed as described above.

【0017】実施例2 次に,上記実施例1に示したプリント配線基板の製造方
法につき,図3〜図8を用いて説明する。まず,図3に
示すごとく,ガラスエポキシ銅張積層基板等の有機系樹
脂基板90を準備する。該有機系樹脂基板90は,上下
面に銅箔層99を有する。次いで,図4に示すごとく,
該有機系樹脂基板90において,電子部品搭載部分にザ
グリ加工より凹部91を形成する。また,スルーホール
92を穿設する。上記凹部91は垂直壁面915を有し
ている。また,上記凹部91の内壁,スルーホール92
の内壁には,前記図12に示すごとく,多数の繊維93
がヒゲ状に露出している。
Example 2 Next, a method of manufacturing the printed wiring board shown in Example 1 will be described with reference to FIGS. First, as shown in FIG. 3, an organic resin substrate 90 such as a glass epoxy copper clad laminated substrate is prepared. The organic resin substrate 90 has copper foil layers 99 on the upper and lower surfaces. Then, as shown in FIG.
In the organic resin substrate 90, a recess 91 is formed in the electronic component mounting portion by counterboring. Further, through holes 92 are formed. The recess 91 has a vertical wall surface 915. In addition, the inner wall of the recess 91 and the through hole 92
As shown in FIG. 12, the inner wall of the
Is exposed like a mustache.

【0018】次に,図5に示すごとく,上記スルーホー
ル92及び凹部91内にスルーホールメッキ層1を被覆
する。次に図6に示すごとく,有機系樹脂基板90の表
面に感光性樹脂被覆4を貼着して,所望の回路パターン
を形成し,その後エッチングを施して図7に示すごとく
導体回路96を形成する。次に,図8に示すごとく,上
記凹部91のスルーホールメッキ層1の表面に金メッキ
層2を形成し,本発明にかかるプリント配線基板10を
作製する。上記のごとく,本例によれば,実施例1に示
したごとき,優れたプリント配線基板を製造することが
できる。
Next, as shown in FIG. 5, the through holes 92 and the recesses 91 are covered with the through hole plating layer 1. Next, as shown in FIG. 6, the photosensitive resin coating 4 is attached to the surface of the organic resin substrate 90 to form a desired circuit pattern, and then etching is performed to form a conductor circuit 96 as shown in FIG. To do. Next, as shown in FIG. 8, a gold plating layer 2 is formed on the surface of the through hole plating layer 1 of the recess 91, and the printed wiring board 10 according to the present invention is manufactured. As described above, according to this example, an excellent printed wiring board as shown in Example 1 can be manufactured.

【0019】実施例3 本例は,実施例2の製造方法において,回路パターン及
び導体回路の形成工程(図6,図7)を,変えた例であ
る。これを,図9〜図11を用いて説明する。即ち,上
記実施例2の回路パターン形成工程(図6)において,
図9に示すごとく,感光性樹脂層45によりネガティブ
パターンを形成し,ハンダ,ニッケル,錫,金などの異
金属メッキ(図示略)により,回路パターンを作る。そ
して,該異金属メッキをエッチングレジストとして,図
10に示すごとく,エッチングにより所望の導体回路9
6を形成する。その後は,図11に示すごとく,凹部9
1のスルーホールメッキ層1の表面に金メッキ層2を被
覆する。上記のごとく,本例によれば,実施例2と同様
の効果を得ることができる。
Example 3 This example is an example in which the steps of forming a circuit pattern and a conductor circuit (FIGS. 6 and 7) in the manufacturing method of Example 2 were changed. This will be described with reference to FIGS. 9 to 11. That is, in the circuit pattern forming step (FIG. 6) of the second embodiment,
As shown in FIG. 9, a negative pattern is formed by the photosensitive resin layer 45, and a circuit pattern is formed by different metal plating (not shown) such as solder, nickel, tin, or gold. Then, using the different metal plating as an etching resist, a desired conductor circuit 9 is formed by etching as shown in FIG.
6 is formed. After that, as shown in FIG.
The surface of the through-hole plating layer 1 is coated with the gold plating layer 2. As described above, according to this example, the same effect as that of the second example can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例1におけるプリント配線基板の断面図。FIG. 1 is a cross-sectional view of a printed wiring board according to a first embodiment.

【図2】実施例1におけるプリント配線基板に電子部品
を搭載した状態の断面図。
FIG. 2 is a cross-sectional view of a printed wiring board according to the first embodiment in which electronic components are mounted.

【図3】実施例2の製造方法における有機系樹脂基板の
断面図。
FIG. 3 is a cross-sectional view of an organic resin substrate in the manufacturing method of Example 2.

【図4】実施例2におけるザグリ加工工程図。FIG. 4 is a counterboring process diagram in the second embodiment.

【図5】実施例2におけるスルーホールメッキ層形成工
程図。
FIG. 5 is a process drawing of forming a through-hole plating layer in the second embodiment.

【図6】実施例2における回路パターン形成工程図。FIG. 6 is a process diagram of a circuit pattern forming process according to the second embodiment.

【図7】実施例2における導体回路形成工程図。FIG. 7 is a process diagram of forming a conductor circuit according to the second embodiment.

【図8】実施例2における金メッキ層形成工程図。FIG. 8 is a process drawing of forming a gold plating layer in Example 2.

【図9】実施例3におけるネガティブパターン形成工程
図。
FIG. 9 is a process diagram of forming a negative pattern in the third embodiment.

【図10】実施例3における導体回路形成工程図。FIG. 10 is a process diagram of forming a conductor circuit according to the third embodiment.

【図11】実施例3における金メッキ層形成工程図。FIG. 11 is a process drawing of forming a gold plating layer in Example 3.

【図12】ザグリ加工した凹部及びスルーホールの断面
説明図。
FIG. 12 is an explanatory cross-sectional view of a recessed portion and a through hole which are counterbored.

【符号の説明】[Explanation of symbols]

1...スルーホールメッキ層, 10...プリント配線基板, 2...金メッキ層, 5...電子部品, 51...ボンディングワイヤー, 90...有機系樹脂基板, 91...凹部, 915...垂直壁面, 92...スルーホール, 93...繊維 96...導体回路, 1. . . Through-hole plating layer, 10. . . Printed wiring board, 2. . . Gold plating layer, 5. . . Electronic components, 51. . . Bonding wire, 90. . . Organic resin substrate, 91. . . Recess, 915. . . Vertical wall, 92. . . Through holes, 93. . . Fiber 96. . . Conductor circuit,

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 有機系樹脂基板に電子部品搭載用の凹部
とスルーホールとを設けてなるプリント配線基板におい
て, 上記凹部はザグリ加工により形成された垂直壁面を有す
ると共に該凹部の底面と垂直壁面の全表面及びスルーホ
ールはスルーホールメッキ層を有し,また凹部のスルー
ホールメッキ層の表面は金メッキ層により被覆されてお
り, 上記スルーホールメッキ層及び金メッキ層が,有機系樹
脂基板の内部に浸入した湿気が上記凹部内に浸入するこ
とを阻止していることを特徴とするプリント配線基板。
1. A printed wiring board comprising an organic resin substrate provided with a recess for mounting electronic parts and a through hole, wherein the recess has a vertical wall surface formed by counterboring, and a bottom surface and a vertical wall surface of the recess. All surfaces and through holes have a through hole plating layer, and the surface of the through hole plating layer in the recess is covered with a gold plating layer. The through hole plating layer and the gold plating layer are inside the organic resin substrate. A printed wiring board, characterized in that invading moisture is prevented from infiltrating into the recess.
JP3074134A 1982-10-12 1991-03-13 Printed wiring board Granted JPH0555401A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3074134A JPH0555401A (en) 1982-10-12 1991-03-13 Printed wiring board

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP57178663A JPS5967686A (en) 1982-10-12 1982-10-12 Printed circuit board and method of producing same
JP3074134A JPH0555401A (en) 1982-10-12 1991-03-13 Printed wiring board

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP57178663A Division JPS5967686A (en) 1982-10-12 1982-10-12 Printed circuit board and method of producing same

Publications (2)

Publication Number Publication Date
JPH0555401A true JPH0555401A (en) 1993-03-05
JPH0563941B2 JPH0563941B2 (en) 1993-09-13

Family

ID=26415269

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3074134A Granted JPH0555401A (en) 1982-10-12 1991-03-13 Printed wiring board

Country Status (1)

Country Link
JP (1) JPH0555401A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007096187A (en) * 2005-09-30 2007-04-12 Sanyo Electric Co Ltd Circuit board and its production process
US7728339B1 (en) 2002-05-03 2010-06-01 Calient Networks, Inc. Boundary isolation for microelectromechanical devices
US7737368B2 (en) 2005-09-30 2010-06-15 Sanyo Electric Co., Ltd. Circuit board and method of manufacturing circuit board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7728339B1 (en) 2002-05-03 2010-06-01 Calient Networks, Inc. Boundary isolation for microelectromechanical devices
JP2007096187A (en) * 2005-09-30 2007-04-12 Sanyo Electric Co Ltd Circuit board and its production process
US7737368B2 (en) 2005-09-30 2010-06-15 Sanyo Electric Co., Ltd. Circuit board and method of manufacturing circuit board
JP4562632B2 (en) * 2005-09-30 2010-10-13 三洋電機株式会社 Circuit board and circuit board manufacturing method

Also Published As

Publication number Publication date
JPH0563941B2 (en) 1993-09-13

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