JPH03119239U - - Google Patents
Info
- Publication number
- JPH03119239U JPH03119239U JP2629190U JP2629190U JPH03119239U JP H03119239 U JPH03119239 U JP H03119239U JP 2629190 U JP2629190 U JP 2629190U JP 2629190 U JP2629190 U JP 2629190U JP H03119239 U JPH03119239 U JP H03119239U
- Authority
- JP
- Japan
- Prior art keywords
- stack
- information processing
- processing device
- memory access
- upstream stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000011144 upstream manufacturing Methods 0.000 claims description 3
- 230000010365 information processing Effects 0.000 claims 2
- 230000006870 function Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 230000003068 static effect Effects 0.000 description 1
Description
第1図はこの考案の一実施例によるパイプライ
ンの上流におけるデリフアレンスの際の構成図、
第2図はこのような方式が必要とされる問題点を
説明する流れ図、第3図は従来のパイプラインマ
シンの構成図、第4図はこの考案によるデリフア
レンスの流れ図、第5図は従来構成によるデリフ
アレンスの流れ図である。
1……メモリアドレスレジスタ、2……メモリ
データレジスタ、3……スタツクトツプポインタ
、4……制御回路、5……アドレスバス、6……
データバス、7……制御バス、8……本考案によ
る比較回路、9,10,11……別のステージの
メモリアドレスレジスタである。なお、図中、同
一符号は同一、又は相当部分を示す。
FIG. 1 is a configuration diagram of an embodiment of this invention at the time of differential upstream of the pipeline.
Figure 2 is a flowchart explaining the problems that require such a system, Figure 3 is a diagram of the configuration of a conventional pipeline machine, Figure 4 is a flowchart of the difference created by this invention, and Figure 5 is a diagram of the conventional configuration. FIG. 1... Memory address register, 2... Memory data register, 3... Static top pointer, 4... Control circuit, 5... Address bus, 6...
Data bus, 7... Control bus, 8... Comparison circuit according to the present invention, 9, 10, 11... Memory address registers of other stages. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
下流ステージ相方で同一のメモリアクセスを行い
、上流ステージにおいてポインタデータの連鎖を
たぐるいわゆるデリフアレンス機能を有し、主記
憶は動的に伸縮するスタツクにより構成される情
報処理装置において、上流ステージのメモリアク
セス時にそのアドレスとスタツクの上限を比較す
る比較器を備え比較結果によりメモリアクセスを
停止することを特徴とする情報処理装置。 Has a pipeline control mechanism, upstream stage,
In an information processing device, the downstream stage performs the same memory access and the upstream stage has a so-called differential function that passes through the chain of pointer data, and the main memory is composed of a stack that expands and contracts dynamically. What is claimed is: 1. An information processing device comprising: a comparator that sometimes compares the address with an upper limit of a stack; and stopping memory access based on the comparison result.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2629190U JPH03119239U (en) | 1990-03-15 | 1990-03-15 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2629190U JPH03119239U (en) | 1990-03-15 | 1990-03-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03119239U true JPH03119239U (en) | 1991-12-09 |
Family
ID=31529195
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2629190U Pending JPH03119239U (en) | 1990-03-15 | 1990-03-15 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03119239U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007289052A (en) * | 2006-04-24 | 2007-11-08 | Shinwa Kikai:Kk | Method for producing pasta food packed in container so as to be applicable to normal temperature storage |
-
1990
- 1990-03-15 JP JP2629190U patent/JPH03119239U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007289052A (en) * | 2006-04-24 | 2007-11-08 | Shinwa Kikai:Kk | Method for producing pasta food packed in container so as to be applicable to normal temperature storage |
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