JPH03118647A - Data transfer system within main storage device of data processor - Google Patents

Abstract

PURPOSE:To transfer data in a short cycle by securing such a constitution where a CPU sends a memory read request signal to a main memory controller MCU and the MCU writes the data into a main memory MEM in response to a memory write request signal. CONSTITUTION:The data D0 is not read out of a MEM 3 yet in a state where a move control signal MOVEC which shows the transfer of the data D0 to an address A1 from an address A0 within the MEM 3 is kept ON at the rise of a CLKT0. Even under such conditions, the end of a memory reading cycle is reported in advance to a CPU 1 from an MCU 2 at the rise of a CLKT2 via a signal TERM. Then the CPU 1 decides that the transfer of data is finished in the MEM 3 and turns off the signal MOVEC at the rise of a CLKT6. Then the MCU 2 starts a signal RAS at the rise of a CLKT7 and after the precharge time of the MEM 3 is over. Then the CPU 1 starts a column address strobe signal CAS at the fall of a CLKT8 and controls the write to the MEM 3. Thus the CPU 1 performs the reading/writing processes in 6 cycles.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer method in a data processing device, and particularly to a data transfer method within a main memory device.

[Conventional technology]

Referring to FIG. 3, the conventional data processing device includes a central processing unit (CPU) 1, a main memory control unit (MCU) 2,
Main memory device (MEM) 3 and main memory address latch (
AL) 4 and a main memory data latch (AL) 5. The CPUI sends a memory read request signal RR to the MCU2.
EQ or memory write request signal WREQ is supplied. In response to memory read request signal RREQ or memory write request signal WREQ, MCU2 sends out MEM3 row address strobe signal RAS and column address strobe signal CAS. When the memory cycle ends, the MCU 2 sends a memory cycle end signal TERM to the CPUI.

The address is transferred from CPU1 to address bus ABo,
It is latched into L4 and output to address bus AB of MEM3. When writing data, the data is transferred from the CPUI to the data bus DB, is latched to DL5, is output to the data bus DBl of the MEM3, and is written to the MEM3.

Data reading goes through the reverse bus. The CPUI is
It has a work register (not shown).

Next, with reference to FIG. 4, a data transfer method within the main storage device by the conventional data processing apparatus shown in FIG. 3 will be described. In the CPU, it is determined whether the instruction in question is an instruction related to data transfer within the main memory device by an operation code branch.

If so, the logical address (virtual address) is translated to a physical address (real address) to prepare for data transfer within main memory.

At the rising edge of CLKTO, read control is activated, the memory read request signal RREQ is turned on, and address A0 is output to address bus AB0, and at the rising edge of CLKTI, it is latched by AL4 and output to address bus AB. At the same time, CLKT.

The row address strobe signal RAS is activated at the rising edge of CLKT, and the column address strobe signal CAS is activated at the falling edge of CLKT. As a result, the read data D0 is output to the data bus DBr at the falling edge of CLKT), latched to DL5, and output to the data bus DBO at the rising edge of CLKT4, and taken into the CPUI. As a read cycle end process, the memory cycle end signal TERM is turned on at the rise of CLKT, and the read cycle ends in five cycles.

After that, after data is stored in the work register by internal processing of the CPU 1, write control is activated at the rising edge of CLKT, memory write request signal WREQ is turned on, address AI is output to address bus AB, and CLKT is
, is latched by AL4 at the rising edge of address bus AB.
, is output to.

At the same time, the row address strobe signal RAS is activated at the rising edge of CLKT, and the column address strobe signal CAS is activated at the falling edge of CLKT-+2. Write data p. is output to the data bus DB at the rising edge of CLKT, is latched by AL4 at CLKT, and is output to the data bus DBI and written into MEM3. As the end processing of the write cycle, CL K T-+
At the rising edge of y, the memory cycle end signal TERM is turned on, and the write cycle ends in four cycles.

Assuming n-w-5, 10 cycles are required from read to write.

In this way, in the conventional data processing device, data transfer in the main memory is performed by reading data D0 from address 80 in MEMB and writing it to the work register in CPUI.
Thereafter, data D0 was written from the work register in CPU1 to address A in MEMB.

[Problem to be solved by the invention]

In the conventional data transfer method in the main memory described above, when data is transferred from one address in the main memory to another address, it passes through the work register in the central processing unit, so unnecessary data is transferred. The disadvantage is that it takes time.

Therefore, an object of the present invention is to speed up data transfer in main memory by transferring data from one address in main memory to another address without passing through the work register in the central processing unit. It's about doing things.

[Means to solve the problem]

A data transfer method within a main memory of a data processing device according to the present invention is a data transfer method in which data is transferred from a first address to a second address within the main memory, in which the central processing unit is transferred to the main memory controller. Sending out a memory read request signal and sending the first address to the main storage device, and the main storage control device reads the main storage device from the first address to the main storage device in response to the memory read request signal. controlling the data to be read, the central processing unit sends a memory write request signal to the main memory control unit and the second address to the main memory unit, and the main memory control unit sends the memory write request signal to the main memory control unit. In response to a request signal, the main memory device stores the read data in the second memory device.
control to write to the address.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

Referring to FIG. 1, a data processing device to which a data transfer method according to an embodiment of the present invention is applied has a CPU with Me.
It has the same configuration as that shown in FIG. 3, except that it sends a move control signal MOVEC indicating that a data transfer command in MEMB is being executed to O2.

Hereinafter, with reference to FIG. 2, a data transfer method within the main storage device by the data processing apparatus of the present invention shown in FIG. 1 will be described.

At the rising edge of CLKTo, the read control is activated, the memory read request signal RREQ is turned on, and the address A0 is output to the address bus A B o, and at the rising edge of CLKTI, it is latched into Al1 and output to the address bus A B l. Ru. At the same time, the row address strobe signal RAS is activated at the rising edge of CLKT'+, and the column address strobe signal CAS is activated at the falling edge of CLKT2. As a result, read data D. is output to data bus DB at the falling edge of CLKT, and latched to DL5.

Address A in MEMB. Data D from address A to address A. Move control signal MOVEC indicating that the
is turned on from the rising edge of CLK T o, and even though data D0 has not been read from MEM3, at the rising edge of CLK T2, the CPU I
A memory read cycle completion report is reported in advance by a memory cycle completion signal TERM.

After that, the CPU turns on the memory write request signal WREQ to start write control at the rising edge of CLKT3, and the address A1 is output to the address bus AB, and at the rising edge of CLKT4, it is latched to Al1 and transferred to the address bus AB. Output to +. Even though data D0 is not written to MEM3, at the rising edge of CLKT5,
A memory write cycle completion report is previously reported from MeO2 to the CPUI using a memory cycle end signal TERM.

CPUI assumes that the data transfer in MEMB has been completed, and transmits the move control signal M at the rising edge of CLKT6.
Turn off OVEC. After that, the CPUI executes the next instruction, but MeO2 waits for the precharge time of MEM3, activates the row address strobe signal RAS at the rising edge of CLKT7, and activates the column address strobe signal CAS at the falling edge of CLKT8. Start up and MEM3
Performs write control for .

In this way, the CPUI completes the read/write process in six cycles.

〔Effect of the invention〕

As described above, the present invention has the advantage that data transfer in the main memory can be performed in a shorter number of cycles than before by displaying the status indicating that data is being transferred in the main memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a data processing device to which a data transfer method according to an embodiment of the present invention is applied, and FIG. 2 is a block diagram showing the main memory of the data processing device of the present invention shown in FIG. 3 is a block diagram showing the configuration of a data processing device to which the conventional data transfer method is applied, and FIG. 4 is a time chart for explaining the data transfer method.
2 is a time chart for explaining a data transfer method within a main storage device by the conventional data processing device shown in the figure. 1... Central processing unit (CPU), 2... Main memory control unit (MCU), 3... Main memory device (MEM)
, 4... Address latch (AL), 5... Data latch (DL). ci (y S and 2 Mi 2 Mi 罎 and (j (< OO and ≧ ト 0 Tsukumi no Ku

Claims (1)

[Claims] 1. In the main memory, data is transferred from a first address to a second address.
In the data transfer method, the central processing unit sends a memory read request signal to a main memory control unit, and also sends the first address to the main memory unit, and the main memory control unit sends the first address to the memory read request signal. The main storage device is controlled to read the data from the first address in response to the request signal, and the central processing unit sends a memory write request signal to the main storage control device and reads the data from the second address. the main storage controller sends the read data to the second main storage device in response to the memory write request signal.
A data transfer method within the main memory of a data processing device that controls writing to addresses. 2. A data transfer system within a main memory device of a data processing device according to claim 1, wherein the central processing unit supplies a signal indicating this to the main memory control device during data transfer within the main memory device. 3. The main storage control device reports the completion of the read cycle to the central processing unit before the read processing to the main storage device ends, and before the write processing to the main storage device ends. 2. The data transfer system in a main memory of a data processing device according to claim 1, wherein the completion of a write cycle is reported to the central processing unit in advance.