JPH03191479A - Image processor - Google Patents

Abstract

PURPOSE:To smoothly process two processing in parallel by executing the 2nd processing only at the time of deciding the end of the 1st processing by comparing the sizes of two addresses stored in a register. CONSTITUTION:Image data to which the 1st processing is applied by an image processor(IMP) 21 is processed by the 2nd processing by means of an IMP 31. In the case of executing the series of image data processing, an address to be written when the IMP 21 executes writing operation in an image memory 41 is stored in an address register 24. At the time of reading out image data from the memory 41 by the IMP 31, the address of the image data to be written is compared with the address stored in the register 24 by a comparator 51 to decide that the 1st processing has been already completed or not. Only at the time of deciding the end of the 1st processing by the control of a bus control part 52 based upon the decided result of the comparator 51, the 2nd processing based upon the IMP 31 can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device having a plurality of image processing processors.

[Prior Art] FIG. 2 shows a conventional example of the image processing device.

This image processing device includes two image processing processors 11.2 and these image processing processors 1 and 2.
In the figure, reference numeral 5 denotes a host hcPU that serves as a data path between the host CPU 3 and each of the processors 1 and 2. Reference numeral 6 designates an image memory bus serving as a data path between each processor 12 and the image memory 4.

FIG. 3 shows the structure of image data on the image memory 4. As shown in FIG.

The two image processing processors 1 and 2 are host CPUs.
3 receives instructions for the source image area I and resultant image area ■ on the image memory 4, and further receives instructions from the host CPU 3.
When it receives a start instruction from the host CPU 3, it starts up, reads the image data A of the source image area (3) instructed by the host CPU 3, and processes that data (this process means enlarging, reducing, and other processing on the image data). ) and writes the processed image data B to the result image area H instructed by the host CPU 3. When the writing is completed, the host CPU 3 is notified of the end of the process by an interrupt.

Note that the areas A and B designated by the host CPU 3 are defined by the start address of the corresponding area, the horizontal size (X), and the vertical size (y).

By the way, in an image processing device having a plurality of image processing processors, each image processing processor handles different processing, and one image processing processor performs the first processing on the image data, while the other image processing processors perform the first processing on the image data. There are cases where the image processing processor executes image data processing that performs second processing.

Taking the above-mentioned conventional example as an example, the image processing processor 1
This is a case where the image processing processor 2 performs the second processing on the image data that has been subjected to the first processing.

However, in general, each image processing processor has a different processing speed, so if you simply execute parallel processing,
There is a possibility that an inconvenience may occur in which the image processing processor 2 starts the second processing even though the first processing by the image processing processor 1 is not completed.

Therefore, in the conventional case, the host CPU 3 first causes the image processing processor 1 to execute the first process, waits for notification of the completion of the process from the processor 1, and then causes the image processing processor 2 to start the second process. ing.

FIG. 4 shows an operation example in which two image processors 1 and 2 access the image memory 4, where read 1 is read by processor 1.
Write 1 is a write operation by processor I, Read 2 is a read operation by processor 2, and Write 2 is a write operation by processor 2.

Also, arrow A indicates the time when the host CPU 3 started the image processing processor 1, arrow exit shows the time when the image processing processor 1 sent a termination notification to the host CPU 3, and arrow c indicates the time when the host CPU 3 started the image processing processor 2. The second arrow indicates the time when the image processing processor 2 sent the completion notification to the host CPU 3.

E Problems to be Solved by the Invention] However, the method in the conventional apparatus is so-called serial processing, as shown in FIG. 4, when the image processing processor 1 reads one or several words of image data, the image The process from processing the data inside the processing processor l to writing the processed image data to the image memory 4 is said to increase the processing time because the image memory 4 is not accessed by any image processing processor. There was a problem.

The present invention has been made in view of the above-mentioned circumstances, and is an image processing apparatus equipped with a plurality of image processing processors. To provide an image processing device capable of shortening a series of processing times by processing the first processing and the second processing in parallel when the second processing is performed by an image processing processor. With the goal.

[Means for Solving the Problems] An image processing device according to the present invention includes a plurality of image processing processors, a host CPU that issues instructions to these image processing processors, and an image memory that stores image data. Each of the image processing processors described above reads the image data of the source image area on the image memory specified by the host CPU, performs certain processing, and transfers the processed image data to the image memory specified by the host CPU. The result is stored in the image area.

A characteristic configuration is that when performing a series of image data processing in which image data that has been subjected to first processing by one image processing processor is subjected to second processing by another image processing processor, the following ( This means performing the processes 1) to (3).

(1) When the first image processing processor writes the image data that has undergone the first processing into the image memory,
The address of the result image area on the image memory instructed by the host CPU is stored in a register (.

(2) When the above-mentioned image processing processor reads the image data to be subjected to the second processing from the image memory,
By comparing the address of the source image area on the image memory to be read with the address stored in the register, it is determined whether the first process has already been completed.

(3) Only when it is determined that the first processing has already been completed, the processing by the image processing processor of the above function is executed.

[Operation] The image processing device according to the present invention is equipped with a plurality of image processing processors, and the image data that has been subjected to the first processing by one image processing processor is processed by another image processing processor. When performing a series of image data processing to perform the second processing, when the first image processing processor performs a writing operation to the image memory, the write destination address is stored in a register.

When the functional image processing processor reads image data from the image memory, it compares the address of the image data to be read with the address stored in the register to determine whether the first processing has already been completed. Determine whether or not the

Then, only when it is determined that the first processing has already been completed, the second processing by the image processing processor of the function is performed.
Execute the process.

Therefore, even if the processing speed of another image processing processor that executes the second processing is faster than that of the first image processing processor that executes the first processing,
It is possible to reliably prevent inconveniences such as the second process starting before the second process is completed, and the first process and the second process can be smoothly processed in parallel, reducing the series of processing times. can do.

[Embodiment] FIG. 1 is a block diagram showing the configuration of an embodiment of an image processing apparatus according to the present invention, and FIG. 5 shows a time chart of the embodiment.

First, all the components of one embodiment will be briefly explained based on FIG. 1, and then the functions and operations of each component will be explained in detail.

In FIG. 1, numerals 21 and 31 are both image processing processors (hereinafter referred to as IMF), and numeral 11 is a host C that outputs the above-mentioned processors 21 and 31.
12 is a host CPU bus serving as a data path between the CPU II and the IMP 21.31.

Reference numeral 41 is an image memory for storing image data;
01 is a memory data bus (hereinafter referred to as MD bus) connected to the image memory 41 as a path for image data, and 402 is a memory data bus connected to the image memory 41 as a path for address data.
This is a memory address bus (hereinafter referred to as the MA bus) connected to the MA bus.

Reference numeral 201 is an address/data bus of the IMP 21, and this address/data bus 201 is connected to the MD bus 01 via a data bus driver 22 and to the MA bus 02 via an address latch register 23. has been done.

Reference numerals 203 to 205 are all signals output from the 1MF 21 to the bus control unit 52, 203 is a read output signal output during a read operation, 204 is a write output signal output during a write operation, and 205 is a signal output from the 1MF 21 to the MD bus 01 and This is a bus request signal output to use the MA bus 02.

Reference numeral 206 is a response signal sent to the 1MF 21 by the bus control unit 52 that has received the bus request signal 205 described above.

Further, reference numeral 301 is an address/data bus of the TMP 31, and this address/data bus 301 is connected to the MD bus 01 via a data bus driver 32, and is connected to the MD bus 01 in turn via an address latch register 33 and an address driver 34. and is connected to the MA bus 02.

Reference numerals 303 to 305 are all signals output from the 1MF 31 to the bus control unit 52, 303 is a read output signal output during a read operation, 304 is a write output signal output during a write operation, and 305 is a signal output from the 1MF 31 to the MD bus 01 and This is a bus request signal output to use the MA bus 02.

Reference numeral 306 is a response signal sent to the 1MF 31 by the bus control unit 52 that has received the above-mentioned bus right request use 305.

Further, reference numerals 208, 209, 308, and 309 are all enable signals output by the bus control section 52 described above, and by receiving these signals, the address latch 23, data bus driver 22, address latch 33,
Data bus driver 32 outputs a predetermined signal.

Further, when the reference numeral 24 receives the set signal 210 from the bus control unit 52, the address latch register 24
Specifically, when the 1MF 21 stores image data that has undergone predetermined processing in the image memory 41, it receives the set signal 210, The address of the resulting image area on the image memory 41 specified by the CPU II is saved.

The address stored in this register 24 is
1 to the comparator 51.

This comparator 51 is processed by the 1MF 21 and the image memory 4
When the 1MF31 performs a read operation on the image memory 41 in order to read and process the image data stored in the 1MF31, the address of the source image R area on the image memory 41 to be read by the 1MF31 and the register 2
By comparing the size with the address stored in 4,
This is to determine whether the processing in the 1MF 21 has already been completed.

In this comparator 51, the address on the image memory 41 of the image data that the 1MF 21 has already finished processing is received from the signal path 211 described above, but the address on the image memory 41 from which the 1MF 31 will read the image data from now on is received from the address latch 33. Signal loss 1ﾾeΔ? Then, this comparator 51 turns on the output signal only when the value of the address stored in the register 24 is larger than the value of the address of the source image area on the image memory 41 to be read by the 1MF 31. Make it. The output signal of this comparator 51 is then output to the OR gate 54 via a signal path 501.

The OR gate 54 controls whether the signal of the comparison H5x is valid or invalid using a signal from a register 53 to which predetermined data is set by the CPU II.
The output is sent to the bus controller 52 via a signal path 502.

Next, the functions and operations of each of the above-mentioned components will be explained in detail.

The IMF 21 transfers data from the CPU II to the image memory 41.
It receives the instructions for the source image area I and the result image area ■ above, and when it receives a start instruction from the CPU II, it starts up and starts the source image area ■ specified by the CPU II.
Read image data A; λi A /l'15-
#? kn! / 7 Mh bar 1m1
−)? + indicates processing of other image data) and writes the processed image data B to the result image area H instructed by the host CPU II. Then, when the writing is completed, the host CPU II is notified of the end of the processing by an interrupt.

Note that the areas A and B specified by the CPU II are defined by the start address of the corresponding area, the horizontal size (X), and the vertical size (y).

The IMF 31 executes processing different from the IMF 21, and there are cases in which the IMF 31 executes processing on image data that has been processed by the IMF 21, and cases in which it processes image data in which the IMF 21 is not involved.

When processing image data in which 1MF21 is not involved, IMF31 uses CP as in the case of 1MF21 described above.
Receives instructions for the source image area ■ and resultant image area H on the image memory 41 from the UII, and further receives instructions from the CPU
When it receives a start instruction from I, it starts up, reads the image data A of the source image area (■) instructed by CPU II, and processes that data (this process means enlarging, reducing, and other processing on the image data). ) and writes the processed image data B to the result image area H instructed by the host CPU II. Then, when the writing is completed, the host CPU II is notified of the end of the processing by an interrupt.

When the IMP 31 processes image data that does not involve the 1MF 21, both IMPs:
By having one IMF execute processing at the appropriate time on the condition that the other IMP is not accessing the image memory 41 (the other IMP's bus request signal is turned off), parallel processing can be performed without any problems. It can be performed.

However, if the processing of IMF31 must use the image data processed by 1MF21, 1MF21
If parallel processing is easily executed only on the condition that the IMFs are not accessing the image memory 41, problems may occur due to differences in the processing speeds of the respective IMFs.

Therefore, in the image processing device of this embodiment, 1MF
IMF3 on the image data subjected to the first processing by 21.
1 must execute the second process, the following processes (1) to (3) are executed in order to prevent problems from occurring.

(1) When the 1MF 21 writes the image data that has undergone the first processing into the image memory 41, the address of the result image area H on the image memory 41 instructed by the Cpuz is stored in a register.

(2) When the IMF 31 reads image data to be subjected to second processing from the image memory 41, the size of the address of the source image H area 1 on the image memory 41 to be read and the address stored in the register is determined. By comparing , it is determined whether the first process has already been completed.

(3) Only when it is determined that the first process has already been completed, the process by the IMP 31 is further executed on the condition that the 1MF 21 has not accessed the image memory 41.

The processes (1) to (3) above will be explained using specific examples.

Here, this specific example is a case where the 1MF 21 writes image data that has undergone predetermined processing into the image memory 41, and immediately after that, the IMF 31 executes reading.

NMP21 write operation J 1MF21 write operation is as follows (wl) to (W5)
The process ends by executing the processes in order.

(Wl) When the 1MF 21 performs a write operation, it first turns on the write output signal 204 and outputs the bus request signal 205 to the bus control unit 52 . Bus control section 5
2 sends a response signal 206 to 1MF21.

(W2) Next, by receiving the response signal 206, the IMF 2J sets the CPUI to the address/data bus 2°1.
Outputs the address specified by I. And 1MF
An address strobe signal 202 sent from the address strobe signal 202 causes the address latch register 23 to latch the address, and then write data is output to the address/data bus 201.

(W3) The bus control unit 52 turns on the enable signal 208 of the address latch register 23 and the enable signal 209 of the data bus driver 22 only when the 1MF 31 is not accessing the image memory 41, and and causes the MD bus 01 to output addresses and data.

The bus control unit 52 also controls the image memory 4I of the 1MF21.
The address storage register 2 recognizes from the write output signal 204 that the access to is a write operation.
4, the set signal 210 is turned on, and the address output to the MA bus 02 is stored in the register 24.

(W4) When the write operation to the image memory 41 is completed, the bus control unit 52 issues a memory access completion response 207 to the 1MF 21, and sends enable signals 208, 20
Turn off 9.

(W5) The 1MF21 turns off the bus request signal 205, the bus control unit 52 turns off the response signal 206, and the write process for the result image area instructed by the CPU II is completed, and the next 1MF31 Shift to reading operation.

``Reading operation of rIMP31'' The reading operation of iMP31 is as follows (R1) to (R6).
The process ends by executing the processes in order.

(R1) First, when the 1MF 31 performs a read operation, it turns on the read output signal 303 and outputs the bus request signal 308 to the bus control unit 52.

The bus control unit 52 sends the response signal 306 to 1M
Send to F31.

(R2) The 1MF 31 receives the response signal 306 and outputs the address instructed by the CPU II to the address/data bus 301.

Then, the address strobe signal 302 sent from the 1MF 31 causes the address latch register 33 to latch the address.

(R3) The output of the address latch register 33 is compared with the output of the address storage register 24 by the comparator 51, and only when the output of the address storage register 24 is larger, the output signal of the comparator 51 is ""on".

The output signal of comparator 51 is input to OR gate 54.

The output signal of the OR gate 54 remains "on" unless both the outputs of the comparator 5I and the register 53 become "off", and is sent to the bus control unit 52.

Here, the output signal of the register 53 is sent to the CPU 1.
When the 1MF 31 processes the image data processed by the 1MF 21, it is turned off, and otherwise it is turned on.

Therefore, the output of the OR gate 54 is "on" or "off" depending on the determination result by the comparator 51 only when the 1MF 31 processes the image data processed by the 1MF 21, and in other cases. is always on.

Only when the 1MF 31 processes the image data processed by , it is used for cultivation purposes.

(R4) The bus control unit 52 recognizes from the read output signal that the access to the image memory 41 by the 1MF 31 is a read operation. And 1MF
21 is not accessing the image memory 41 (the bus request signal 205 is off) and the output signal of the OR gate 54 is on, the address bus driver 34 and the data bus driver 32 are Turn on enable signals 309 and 308 of 1MF31.
access to the image memory 41 of.

Note that when the output signal of the OR gate 54 is off, the O
1MF31 until the output signal of R gate 54 turns on.
The reading operation into the image memory 41 is suspended.

(R5) When the reading operation of 1MF31 for the image memo 1,141 is completed, the bus control unit 52 controls the 1MF31
A termination response 307 is issued in response to the request, and the outputs of the enable driver 32 and address driver 34 are turned off.

(R6) The 1MF 31 turns off the bus request signal 305, the bus control unit 52 turns off the response signal 306, and
The read operation for the source image area instructed by the PUII is completed, and the process moves to the next read operation by 1MF21 or write operation by 1MF31.

FIG. 5 shows that after the write operation of 1MF21, 1MF31
This figure shows a timing chart when executing a read operation.

In FIG. 5, (a) shows the bus request signal 205, (b)
) is the response signal 206 to the bus request signal 205, (
C) is the data on the address/data bus 201, (d) is the address strobe signal 202 to the address latch register 23, (e) is the enable signal 208 to the address latch register 23, and (f) is the data bus driver 22.
(g) is the set signal 210 of the register 24, (h) is the address signal sent to the signal path 211, and (i) is the memory access completion response signal 207 sent to the 1MF 21.

Further, (j) is the bus request signal 305, (k) is the response signal 306 to the bus request signal 305, (1) is the data on the address/data bus 301, and (m) is the address stroke to the address latch register 33. -7' signal 302
, (n) from the address latch register 33 to the comparator 51
(0) is the output signal of the comparator 51 on the signal path 501, (p) is the read output signal 303 indicating the read operation, (q) is the enable signal for the address driver 34. 308, (r)
is the enable signal 30 for the data bus driver 32
9, (S) is a memory access completion response signal 307 sent to the 1MF31.

When 1MF31 uses the image data processed by 1MF21, the output signal of OR gate 54 is as shown in FIG.
It matches the output signal of the comparator 51 shown in 0).

Arrows T, , T, , T3 in this FIG. T,,T,.

T, ,T, ,T, ,T, all indicate corresponding timing points between,signals.

In Fig. 5, the period indicated by the symbol ■ is 1MF2
1 is the write cycle, and the period indicated by ■ is 1MF.
This is a read cycle according to No. 31.

The IMF 21 repeats the operations (W I ) to (W5) described above every time the CPU II designates the result image area (2). In addition, the 1MF 31 performs the above-mentioned (R1) to (R6
)repeat.

Note that in the above-mentioned specific example, the read operation by 1MF21 and the write operation by 1MF31 are not explained, but the access procedures during these operations are the same as in the conventional case (that is, when the other IMF The process is executed on the condition that the process is not being accessed), so the explanation will be omitted.

And 1MF21 and 1MF31 are both C
When the read and write operations are completed for all areas instructed by the PUII, a completion notification is sent to the CPUII.

As is clear from the above description, in the image processing apparatus of the above-mentioned embodiment, the image data that has been subjected to the first processing by the 1MF21 is processed by the IMP31 for the second processing.
When performing a series of image data processing, first, when the 1MF 21 performs a writing operation to the image memory 41, the write destination address is stored in the register 24.

When the 1MF 31 reads image data from the image memory 41, a comparator 51 compares the address of the image data to be read and the address stored in the register 24.
By comparing the sizes at , it is determined whether the first process has already been completed.

Then, the bus control unit 5 based on the determination result of the comparator 51
The second process by the 1MF 31 becomes executable only when it is determined that the first process has already been completed.

Therefore, in the image processing device of the above embodiment, the second
Even if the 1MF31 that executes the 1st process has a faster processing speed than the 1MF21 that executes the 1st process,
It is possible to reliably prevent inconveniences such as the second process starting before the first process is finished, and to smoothly process the first process and the second process in parallel, thereby reducing the series of processing times. can be shortened.

In the above-mentioned specific example, it was assumed that the read operation of the rMP 31 is interrupted immediately after the fMP 21 performs the write operation, but the timing at which the read operation of the 1MF 31 is interrupted is not limited to this specific example. For example, if the 1MF 21 has already finished the write operation, which is the first process, the reading of the IMP 31 can be interrupted immediately after the subsequent reading operation of the 1MF 21 is finished.

FIG. 6 shows a case where the first read operation of the 1MF 31 is interrupted after the 1MF 21 has finished the first read operation and write operation and further finished the second read operation.

In FIG. 6, read 1 indicates a read operation by 1MF21, write 1 indicates a write operation by 1MF21, read 2 indicates a read operation by 1MF31, and write 2 indicates a write operation by 1MF31.

Also, arrow ho is the time when CPU II started 1MF21, arrow to is the time when CP Indicates when the notification was sent.

In the above-described embodiment, an image processing apparatus including two image processing processors is shown, but it goes without saying that the present invention can also be applied to an image processing apparatus including three or more image processing processors. It can also be applied to cases in which three or more image processing processors are used to sequentially perform processing.

[Effects of the Invention] As is clear from the above description, the image processing device according to the present invention is equipped with a plurality of image processing processors, but the first processing is performed by one image processing processor. When executing a series of image data processing in which image data is subjected to second processing by another image processing processor, when the first image processing processor performs a writing operation to the image memory, the writing destination address is Store it in a register.

When the other image processing processor reads image data from the image memory, it compares the address of the image data to be read with the address stored in the register to determine whether the first processing has already been completed. Determine whether or not the

Then, only when it is determined that the first processing has already been completed, the second processing by the other image processing processor is performed.
Execute the process.

Therefore, in the image processing apparatus of the present invention, the other image processing processor small h (compartment 1) that executes the second processing is
Even in cases where the processing speed is faster than the image processing processor in the F-10, it is possible to reliably prevent the inconvenience of starting the second process before the first process is completed. The first processing and the second processing can be smoothly performed in parallel, and the series of processing times can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a schematic configuration diagram of a conventional image processing device, FIG. 3 is an explanatory diagram of the configuration of an image memory in the image processing device, and FIG. 4 is an image of a conventional image processing device. FIG. 5 is an explanatory diagram of the operation of the processing device, FIG. 5 is a timing chart of the embodiment, and FIG. 6 is an explanatory diagram of the operation of the embodiment. 11...Host CPU, 2], 31...
・Image processing processor, 22.32... Data bus driver 23.33... Address latch register, 24... Address storage register, 34... Address driver 41...
・Image memory, 51... Comparator, 52...
...Bus control unit, 53...Register, 5a
, , , , , r> p y-b2 Schematic configuration diagram of a conventional image processing device Second drawing Explanatory diagram of the configuration of an image memory FIG. 3

Claims (1)

[Scope of Claims] Each image processing processor includes a plurality of image processing processors, a host CPU that issues instructions to these image processing processors, and an image memory that stores image data. The image data of the specified source image area on the image memory is read, certain processing is performed, and the processed image data is transferred to the host CP.
An image processing device that stores image data in a result image area on an image memory designated by U, wherein image data that has been subjected to a first process by one image processing processor is subjected to a second process by another image processing processor. When executing a series of image data processing to perform the first processing, when the first image processing processor writes the image data that has undergone the first processing into the image memory, the result on the image memory instructed by the host CPU is The address of the image area is stored in a register, and when the other image processing processor reads image data to be subjected to second processing from the image memory, it stores the address of the source image area on the image memory to be read and the above image data. By comparing the size with the address stored in the register, it is determined whether the first process has already finished, and only when it is determined that the first process has already finished, An image processing device characterized by executing processing by the other image processing processor.