JPH0311827A - Error detection and correction circuit - Google Patents

Abstract

PURPOSE:To surely correct both of a frame bit and a parity bit by providing a data comparator circuit fetching input and output data of a frame correction circuit, comparing them and outputting an inverting command when the both are different. CONSTITUTION:A data comparator circuit 8 fetches a data 200 before frame bit correction and a data 300 after frame bit correction, compares them and outputs an inverting instruction 800 when a different bit exists. A parity inversion circuit 10 receiving the instruction inverts a parity data 700 and outputs an inserted data 400 to a parity bit correction circuit 6. On the other hand, the data 300 whose frame bit is corrected outputted from the frame correction circuit 4 is subject to insertion with the data 400 from the circuit 10 as a parity bit. Thus, the result is outputted from the circuit 6 as an output data 500 whose frame bit and parity bit are corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error detection and correction circuit for a digital transmission system, and particularly to an error detection and correction circuit that can correct both frame bits and parity bits.

[Conventional technology]

As shown in FIG. 2, this type of conventional error detection and correction circuit includes a parity check circuit 2 that performs a parity check on input data 100, and a frame pit in the data 200 after the parity check from the parity check circuit 2. A frame correction circuit 4 corrects frame bits when there is an error and outputs the result as output data 300, and parity data from the parity check circuit 2 is reinserted into the data 300 from the frame correction circuit 4 as insertion data 400 and output. The parity bit correction circuit 6 outputs data 500.

According to such an error detection and correction circuit, the parity check circuit 2 calculates parity for the input data 100 and compares the result with the input data 100 to determine whether the input data 100 contains error bits. Determine whether or not there is. The parity check circuit 2 outputs error information 600 when there is an error in the input data 100, and also outputs the parity data 700 and the output data 20.
Outputs 0. In the output data 200 from the parity check circuit 2, correct frame bit data is reinserted in the frame correction circuit 4 in consideration of the case where the frame bits are incorrect. The frame bit-corrected data 300 is processed by the parity bit correction circuit 6 to insert data 400 (parity data 70
0) is inserted as a parity pit and the output data 5
Output as 00.

[Problem to be solved by the invention]

However, in an error detection and correction circuit having such an error detection and correction function, when the input data 100 including an erroneous frame bit is corrected, the parity of the data differs between before and after correction. Therefore, in the conventional error detection and correction circuit, when the parity data 700 detected from the data 100 before frame peer correction is inserted as the parity of the data 300 after frame bit correction, the data 500 becomes the actual parity data. This has the disadvantage that data with uncorrected errors is output as a result.

The present invention has been made to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide an error detection and correction circuit that can reliably and accurately correct both frame bits and parity bits.

[Means to solve the problem]

The error detection and correction circuit of the present invention includes a parity check circuit that performs a parity check on input data, and a frame correction circuit that performs frame bit correction when there is a frame bit error in the data after the parity check from the parity check circuit. and a parity bit correction circuit that reinserts the data from the parity check circuit into the data from the frame correction circuit to obtain output data. A data comparison circuit that compares these and outputs an inversion command when the two differ; and a data comparison circuit that inverts and outputs the parity data from the parity check circuit only when there is an inversion command from this data comparison circuit, and inverts it otherwise. The present invention is characterized in that it includes a parity inversion circuit that outputs the data without changing the parity bit and supplies it to the parity bit correction circuit as insertion data.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the error detection and correction circuit of the present invention. In the embodiment shown in FIG. 1, the same components as those in the circuit shown in FIG. 2 will be described with the same reference numerals.

The error detection and correction circuit shown in FIG. 1 is composed of a parity check circuit 2, a frame correction circuit 4, a parity bit correction circuit 6, a data comparison circuit 8, and a parity inversion circuit 10.

Here, the baritichi s '7 circuit 2 has input data 1
A parity check is performed on 00. The frame correction circuit 4 is configured to perform frame bit correction and output as output data 300 when there is a frame bit error in the data 200 after the parity check from the parity check circuit 2. The parity bit correction circuit 6 is capable of reinserting insert data 400 given from the outside into the data 300 from the frame correction circuit 4 as a parity pit, and outputting output data 500. The data comparison circuit 8 is configured to take in the input data 200 and the output data 300 of the frame correction circuit 4, compare them, and output an inversion command 800 when the two differ. The parity inversion circuit 10 receives an inversion command 800 from the data comparison circuit 8.
The parity data 700 from the parity check circuit 2 is inverted only when
The parity bin correction circuit 6 is configured to receive insertion data 400 formed without inverting 00.

The operation of the embodiment configured in this way will be explained.

The parity check circuit 2 calculates parity for the input data 100 and compares the result with the input data 100 to determine whether the input data 100 includes an error bit. Parity check circuit 2 outputs error information 600 when input data 100 has an error, and also outputs parity data 700 and output data 200. In the output data 200 from the parity check circuit 2, correct frame bit data is reinserted in the frame correction circuit 4 in consideration of the case where the frame bits are incorrect.

Here, the data comparison circuit 8 compares data 200 before frame bit correction and data 300 after frame bit correction.
and compare them, and if there are no different bits (there is no error in the frame bits), use the inversion instruction 8.
Do not output 00. As a result, the parity inversion circuit 10
outputs insertion data 400 formed without inverting parity data 700 to parity bit correction circuit 6.

The data 300 output from the frame correction circuit 4 includes:
In the parity bit correction circuit 6, the insertion data 400 (non-inverted parity data 700) from the parity inversion circuit 10 is inserted as a parity bit. The data thus obtained in the parity bit correction circuit 6 is output as output data 500.

On the other hand, the data comparison circuit 8 takes in the data 200 before frame bit correction and the data 300 after frame bit correction, compares them, and finds different bits (
If there is an error in the frame bits), the inversion instruction 80
Outputs 0. As a result, the parity inversion circuit 10
Insert data 4 formed by inverting parity data 700
00 is output to the parity bit correction circuit 6. The inserted data 400 (inverted parity data 700) from the parity inverting circuit 10 is inserted as a parity bit into the frame bit corrected data 300 output from the frame correcting circuit 4 in the parity bit correcting circuit 6. The data thus obtained in the parity bit correction circuit 6 is output as output data 500.

In this embodiment, output data with frame vias and parity bits corrected as described above is obtained.

〔Effect of the invention〕

As explained above, the present invention compares data before frame bit correction by the frame correction circuit with data after frame bit correction, and inverts or non-inverts previously detected parity data based on the comparison result. By re-inserting the output data at the parity focus, it is possible to correct the frame bits and parity pits and obtain output data even for input data containing erroneous frame bits.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional circuit. 2...Parity check circuit, 4...
Frame correction circuit, 6... Parity bit correction circuit, 8...
Data comparison circuit, 10...Parity inversion circuit.

Claims (1)

[Claims] a parity check circuit that performs a parity check on input data; a frame correction circuit that performs frame bit correction when the data after the parity check from the parity check circuit has a frame bit error; and data from the frame correction circuit. and a parity bit correction circuit for reinserting data from the parity check circuit to obtain output data, the error detection and correction circuit takes input and output data of the frame correction circuit, compares them, and calculates whether the two are correct. a data comparison circuit that outputs an inversion command when different; and a data comparison circuit that inverts and outputs the parity data from the parity check circuit only when there is an inversion command from the data comparison circuit, and otherwise outputs the parity data without inversion. An error detection and correction circuit comprising: a parity inversion circuit that supplies data as insertion data to a parity bit correction circuit.