JPH03117194A - Standard signal discrimination circuit - Google Patents

Abstract

PURPOSE:To discriminate a frequency deviation accurately by switching a standard discrimination signal continuously in a stable way in the case of the standard mode and switching the signal at an interval of an integral number of multiple of frame period in the nonstandard mode when the nonstandard mode is consecutively detected. CONSTITUTION:In the case of special reproduction of a laser disk, for example, the standard signal is selected when a consecutiveness detection circuit 30 detects it that a standard detection signal STD' 211 outputted from a discrimination circuit 27 is discriminated standard consecutively for 15 times by outputting a set signal 212 setting an RS flip-flop 33. When the nonstandard signal is selected when a delay standard detection signal STD'' 213 and the standard detection signal STD' represent the nonstandard by outputting a reset signal 214 resetting the flip-flop 33. Thus, even when the standard detection signal STD' is more or less in error, the standard discrimination signal STD 215 is not selected. As a result, the nonstandard signal is stably detected even when a signal very close to the standard signal reaches.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention utilizes the fact that there is a predetermined relationship between the frequency of a color subcarrier included in an input video signal and a horizontal synchronization signal. The present invention relates to a standard determination circuit that determines whether the input video signal is a standard signal or not.

(Prior art) In recent years, with the rapid development of digital IC technology, home television receivers are also using three
Dimensional video signal processing has become possible.

Through 3D video signal processing using this image memory,
In still image signals, it has become possible to completely eliminate losstalk between luminance signals and color signals, which was impossible with conventional two-dimensional signal processing.

(2) Crosstalk between the luminance signal and chrominance signal caused by this 3D video signal is removed by utilizing the fact that the ratios of the color subcarrier frequency, horizontal frequency, and vertical frequency of the input video signal are in a certain relationship. It is being said.

For example, in an NTSC video signal, if the color subcarrier frequency is fsc, the horizontal frequency is fh, and the vertical frequency is fv, there is a relationship as shown in the following equation.

f sc-(455/2) ・fh f h-(525/2) ・fv However, the video signal input to a home television receiver has color subcarrier frequency, horizontal frequency, and vertical frequency. There are non-standard video signals whose ratios do not have a fixed relationship. For example, this corresponds to a video signal obtained by special playback of a video tape recorder, a television game machine, or a video disc player. If three-dimensional video signal processing is performed on such non-standard signals, the displayed image will deteriorate.

Therefore, if a non-standard signal is input, it is necessary to detect it (3) and switch to two-dimensional video signal processing. Therefore, a circuit is required to determine whether the input video signal is a standard signal or not.

FIG. 3 is a circuit diagram showing the configuration of a conventional standard signal discrimination circuit.

This discrimination circuit utilizes the fact that the ratio between the color subcarrier frequency and the water IP frequency is in a fixed relationship to discriminate whether or not the input video signal is a standard signal.

That is, in FIG. 3, a horizontal reference signal (HREF) 101 whose phase is synchronized with a horizontal synchronization signal included in an input video signal is input to an input terminal 1. Further, a clock signal (CK) 102 is input to the input terminal 2.

This clock signal 102 is phase synchronized with the color subcarrier included in the input video signal and has a frequency four times the frequency of this color subcarrier.

In the NTSC standard signal, horizontal reference signal 1
01 frequency fref and clock signal 102 frequency 4
The following proportional amount (A) holds true between fsc and fsc.

4fsc-910efref The counter 3 counts the clock signal 102 reset by the horizontal reference signal 101.

The timing signal generation circuit 4 outputs a timing signal of a standard horizontal period based on the count output 103 from the counter 3.

The determination circuit 5 uses the output timing signal 104 from the timing signal generation circuit 4 as a mask signal, and masks the horizontal reference signal 101 with this timing signal 104 to determine whether the input video signal is a standard signal or not. be. That is, the discrimination circuit 5 determines that the input video signal is a standard signal when the horizontal reference signal 101 is masked by the timing signal 104, and determines it as a non-standard signal when the horizontal reference signal 101 is not masked. This discrimination signal (STD) 105 is output from the output terminal 6.

As described above, the conventional standard signal discrimination circuit includes a counter 3 that is reset (5) by a predetermined horizontal reference signal 101 and counts a predetermined clock signal 102, and a count output 103 of this counter 3.
By generating a mask signal based on the horizontal reference signal 101 and masking the horizontal reference signal 101 with this mask signal, it is determined whether the input video signal is a standard signal or not.

However, such a configuration has the following problems.

Since the mask signal is generated based on the count output 103 of the 1-tsuba counter 3, 1 water・I' J17J f
The problem with il (IH) is that it is not possible to distinguish small frequency deviations of one clock or less.

The other problem is that if phase fluctuations (jitter) occur in the horizontal reference signal 101, such as when noise is mixed into the input video signal due to disturbances such as weak electrolysis, the standard signal may be mistakenly treated as a non-standard signal. The problem is that it may be mistaken.

(Problem to be Solved by the Invention) As described above, the problem (6) in the conventional standard signal discrimination circuit is that it is not possible to discriminate small frequency deviations of one clock or less in one horizontal period, and the problem is that the horizontal reference signal If phase fluctuation (jitter) occurs in
There is a problem in that a standard signal may be mistakenly determined to be a non-standard signal.

The present invention was made in view of the above circumstances, and includes 1 horizontal 11
．． It is an object of the present invention to provide a standard signal discriminating circuit that can accurately discriminate even a small frequency deviation of one clock or less in llj and that can reduce misjudgment due to phase fluctuation (jitter).

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the standard signal discrimination circuit of the present invention synchronizes with the color subcarrier included in the input video signal and A clock signal having a frequency that is an integral multiple of the frequency, a horizontal timing signal synchronized with the horizontal synchronization signal included in the input video signal, and a vertical timing signal synchronized with the vertical synchronization signal included in the input video signal are input, ) detecting means for detecting that the ratio between the frequency of the color subcarrier and the frequency of the horizontal synchronizing signal is in a predetermined relationship in each diagonal period; A first determining means that determines that the signal is a standard signal and a detection output of the detection means are delayed, and if both the delayed output and the detection output of the detection means are not in a predetermined relationship, the signal is a non-standard signal. The present invention is characterized by comprising a second discriminating means for discriminating, and a standard discriminating means for performing standard discriminating based on the output results of the first discriminating means and the second discriminating means.

(Function) In the device configured as described above, the standard discrimination signal is switched when a stable standard is obtained continuously in the case of the standard, and at intervals of an integral multiple of the frame period in the case of the non-standard. Since this is performed when a non-standard signal is obtained in succession, it is possible to stably detect a non-standard signal even in a signal that is very close to a marker, such as during special playback of one stroke per static laser disc, and, Non-standard signals (8) can be discriminated stably even in the face of phase fluctuations (jitter).

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
FIG. 1 is a circuit diagram showing the configuration of a standard signal discrimination circuit according to an embodiment of the present invention.

The illustrated standard discrimination circuit utilizes the fact that the ratio between the color subcarrier frequency and the horizontal frequency is in a fixed relationship to discriminate whether or not the input video signal is a standard signal.

That is, in FIG. 1, 21 is a clock signal (CK
) 201 is the input terminal. This clock signal 201 is phase-synchronized with the color subcarrier included in the input video signal and has a frequency four times the frequency of the color subcarrier. 22 is a terminal to which a horizontal reference signal (FREF) 202 is input. This horizontal reference signal 202
is a signal whose phase is synchronized with the horizontal synchronization signal included in the input video signal.

In the standard signal of the NTSC system, the frequency 4fsc of the clock signal 201 and the frequency fref of the horizontal reference signal (9) 202 have a proportional relationship as shown in the following equation.

4fsc-910・fref The above clock signal 201 is converted to 9 by the frequency division counter 23.
The frequency is divided by 10. Thereby, the count period of this frequency division counter 23 coincides with the horizontal synchronization when the standard signal is input.

The count output 203 of the frequency division counter 23 is the latch circuit 2
4 and is supplied to the load signal generation circuit 25. The count output 203 supplied to the latch circuit 24 is output to the latch circuit 24 at the input timing of the horizontal reference signal 202.
latched to.

When the standard signal is input, the latch output 204 of the latch circuit 24 shows a constant value because the count period of the frequency division counter 23 matches the horizontal period of the input video signal.

On the other hand, when a non-standard signal is input, the count period and the horizontal period of the input video signal do not match, resulting in fluctuations. The latch output 204 of the latch circuit 24 is the average value circuit 2
6 and is supplied to the discrimination circuit 27.

(lO) The average value circuit 26 integrates the latch output 204 over a period sufficiently longer than one horizontal period, for example.
This latch output 204 is averaged. This averaging operation is performed by timing signal (VSF) 2 input from terminal 28.
It is carried out based on 05. This timing signal 205 is a pulse signal with a vertical period synchronized in phase with the vertical synchronization signal included in the input video signal.

The averaged output 206 of the averaging circuit 26 is supplied to the determination circuit 27 and the load signal generation circuit 25.

The determination circuit 27 is a circuit that determines whether the latch output 204 is within a predetermined variation tolerance range. If the input video signal is not within the allowable range, it is determined that the input video signal is a non-standard signal, and a correction signal 207 is supplied to the load signal generation circuit 25.

The determination circuit 27 also determines whether the averaged output 206 of the averaging circuit 26 is within a predetermined permissible variation range when the latch output 204 is within a predetermined permissible variation range. (Jl) Ru. If it exists, it is determined that the input video signal is a standard signal, and if it does not exist, it is determined that the input video signal (ci) is a non-standard signal.This determination is made based on the timing (3 The timing signal 208 is a vertical synchronization pulse signal whose phase is synchronized with the vertical synchronization signal included in the input video signal.

When the load signal generation circuit 25 is supplied with the correction signal 207 from the discrimination circuit 27, the load signal generation circuit 25 outputs the horizontal reference signal 207.
At input timing 2, a load signal 210 is output.

On the other hand, when the correction signal 207 is not supplied, the load signal 210 is output at a predetermined timing based on the averaged output 206 output from the averaging circuit 26.

Load signal 21 output from load signal generation circuit 25
0 is used as a load signal to load a predetermined count value into the frequency division counter 23. Thereby, the frequency division operation of the frequency division counter 23 is corrected to a predetermined state.

(19) Discrimination output (standard detection signal) of discrimination circuit 27 (STD'
) 211 is the continuity detection circuit 30. Delay circuit 31. and the gate circuit 32, respectively.

The continuity detection circuit 30 detects whether the standard detection signal (STD') 211 continuously indicates the standard. For example, when the standard detection signal (STD") 211 is obtained 15 times in a row, Set signal 21 to
Outputs 2.

The delay circuit 31 delays the standard detection signal (STD') 211 by two frames, and generates a delayed standard detection signal (STD').
2] Outputs 3.

The gate circuit 32 outputs a reset signal only when the delayed standard detection signal (STD') 213 output from the delay circuit 31 and the standard detection signal (STD') 211 output from the discrimination circuit 27 both indicate non-standard. 214 is output.

The RS flip-flop 33 is set by the set signal 212 output from the continuity detection circuit 30, reset by the reset signal (13) 214 output from the gate circuit 32, and outputs a standard detection signal (STD) 215 from the output terminal 34. Output.

Next, the operation in the above configuration will be explained.

Timing signal (VSF) 205. (VSEN)2
08 is a pulse signal output in vertical synchronization in phase synchronization with a vertical synchronization signal included in the input video signal. In this case, the pulse width of the timing signal (VSF) 205 is 1
It is set to 6 horizontal periods. Also, the timing signal (
The pulse width of VSEN) 208 is set to one horizontal period. In addition, this timing signal (VSEN) 208
The phase is set to such a phase that it rises at the fall timing of the timing signal (VSF) 205.

In an initial state such as when the power is turned on, when the horizontal reference signal (I(REF) 202 is input from the terminal 22, the load signal generation circuit 25 outputs the load signal 210. As a result, the frequency division counter 23 receives a predetermined value). The count value is loaded. This count value is set to 512, for example.

(14) If the input video signal is a standard signal, the frequency division counter 23
The latch circuit 24
The latch output 204 of will always be 512. On the other hand, when the input video signal is a non-standard signal, the division period of the frequency division counter 23 does not match the horizontal period, so the latch output 204 of the latch circuit 24 gradually deviates from 512.

The latch output 204 of the latch circuit 24 is averaged by the averaging circuit 26 over 16 horizontal periods for each vertical period. As a result, the latch output 20 of the latch circuit 24
Even if 4 is temporarily shifted by several clocks around 512 due to jitter occurring in the horizontal reference signal (HREF) 202, data that is not affected by either of these factors can be obtained.

As described above, when the latch output 204 of the latch circuit 24 deviates from the permissible variation range within the vertical period, the discrimination circuit 27 outputs the correction signal 207 and discriminates that the input video signal is a non-standard signal. do. Here, the variation tolerance range is set to (15) 504 to 519, for example.

On the other hand, if the input video signal is close to the standard signal and the latch output 204 is within the permissible variation range,
The determination is made using the averaged output 206 of the averaging circuit 26 in which the influence of jitter and the like has been reduced. The permissible variation range in this case is set to 510 to 514, for example.

When the correction signal 207 is supplied from the discrimination circuit 27, the load signal generation circuit 25 generates a load signal 21 at the manual timing of the horizontal reference signal (HREF) 202.
Outputs 0. On the other hand, if the correction signal 207 is not supplied, the error between the averaged output 206 of the averaging circuit 26 and its original value (512) is detected, and the load signal 210 is output at a timing that can eliminate this error. .

As a result, when the power is turned on, etc., the frequency division counter 23
If the deviation of the frequency division operation is large, the frequency division counter 23
The frequency division operation is performed using the horizontal reference signal (HREF) 20
If the deviation is small, the correction is made to the predetermined state based on the averaged output 206 which is less affected by the jitter (16).

In this way, the standard detection signal (STD
) 211 is obtained.

In the case of special reproduction of laser discs, the standard and non-standard states are alternately repeated for each field, and the deviation from the standard signal is less than 140 N5EC per frame.

Therefore, when the electric field of the video signal is weak or there is a large fluctuation in the average level, the state of horizontal synchronization separation changes and the standard detection signal (STD') 211 may be detected incorrectly.

Incidentally, in terms of signal processing, when a non-standard signal is mistakenly detected as a standard signal, the deterioration on the screen is greater than when a standard signal is mistakenly detected as a non-standard signal.

Therefore, in this embodiment, switching to the standard signal is performed when the continuity detection circuit 30 detects that the standard detection signal (STD') 211 output from the discrimination circuit 27 is standard 15 times in a row. A set signal 212 is output to set the RS flip-flop 33 (17) as shown in FIG. This set signal 212 sets the RS flip-flop 33 and outputs a standard discrimination signal (STD) 215 to the output terminal 34.

Therefore, as shown in the signal waveform diagram when the standard detection signal (STD') 211 causes a detection error when the standard signal is input as shown in FIG. 2(b), the standard detection signal (STD')
) 211 is detected incorrectly, the standard discrimination signal (STD) 215 does not switch.

To switch to the non-standard signal, the gate circuit 32 uses the 2-frame delay circuit 31 to delay the standard detection signal (STD'> 211) output from the discrimination circuit 27 by 2 frames and converts the standard detection signal (STD') 213 into a delayed standard detection signal (STD'). and discrimination circuit 2
When both the standard detection signal (STD') 211 output from 7 indicates non-standard, a reset signal 214 for resetting the RS flip-flop 33 is output. This reset signal 214 causes the RS flip-flop 33 to
is reset and the standard discrimination signal (STD) 215 is output to the output terminal (
18) Output to child 34. For this reason, the standard detection signal (ST
D') 211 is incorrect, the standard discrimination signal (STD) 21
5 will never switch.

Moreover, it is possible to effectively detect the special playback of a laser disc.

As mentioned above, the standard discrimination signal is switched when a stable standard is continuously obtained in the case of a standard, and when a stable standard is continuously obtained in the case of a non-standard. Since it is performed when Can distinguish standard signals.

Although one embodiment of the present invention has been described above in detail, the present invention is not limited to this embodiment, and it goes without saying that various other embodiments can be implemented.

[Effects of the Invention] According to the present invention, the standard discrimination signal is switched when a stable standard is obtained continuously in the case of the standard, and when the standard is switched by an integer of the frame period (H's) in the case of the non-standard. Since this is performed when non-standard signals are obtained consecutively at intervals, non-standard signals can be stably detected even in signals that are very close to the standard, such as during special playback of still images on laser discs, and phase fluctuations can be detected. Non-standard signals can be stably discriminated against (jitter).

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a standard signal discriminating circuit according to an embodiment of the present invention, and FIG. 2 is a signal waveform diagram for explaining the operation of the standard signal discriminating circuit according to an embodiment of the present invention. Third
The figure is a circuit diagram showing the configuration of a conventional standard signal discrimination circuit. 21.22.28, 29.34... terminal, 23...
Frequency division counter, 24...Latch circuit, 25...Load signal generation circuit, 26...Averaging circuit, 27...Discrimination circuit, 30...
- Continuity detection circuit, 31...Delay circuit, 32...Gate circuit, 33...RS flip-flop.

Claims (1)

[Claims] (1) A clock signal that is synchronized with the color subcarrier included in the input video signal and has a frequency that is an integral multiple of the frequency of the color subcarrier, a horizontal timing signal that is synchronized with the horizontal synchronization signal included in the input video signal, and a detection means for inputting a vertical timing signal synchronized with the vertical synchronization signal included in the input video signal and detecting that the ratio between the frequency of the color subcarrier and the frequency of the horizontal synchronization signal is in a predetermined relationship for each vertical period. and a first determining means for determining that the signal is a standard signal if the detection output of the detection means is obtained a predetermined number of times in succession; a second discrimination means for determining that the signal is a non-standard signal if both of the detection outputs do not have a predetermined relationship; and standard discrimination is performed based on the output results of the first discrimination means and the second discrimination means. 1. A standard signal discriminating circuit comprising: standard discriminating means.