JPH03113377A - Driving method for indicating instrument - Google Patents

Abstract

PURPOSE:To handle a low frequency input and a high frequency input by comparing the input period of a pulse signal with a set period by a decision part and varying an arithmetic processing period according to the comparison result. CONSTITUTION:Every time the pulse signal (a) generated by the specific quantity variation of an object of measurement is inputted, a constant value is added to an operand value and a specific value is subtracted at a constant period; and the indication of a display part 3 is determined and the display part is driven. At this time, the decision part 16 of a conversion part 1 compares the input period of the pulse signal (a) with the set period. Then a timing generator 12 switches the arithmetic processing period between a long and a short period according to the low frequency input and high frequency input.

Description

[Detailed description of the invention] (Industrial use! I!?) The present invention relates to a method for driving an indicating instrument.

(Prior art) Indicating instruments that convert the display output from the object to be measured into an appropriate electrical signal (frequency, positive N value, etc.) and operate the pointer of the indicating instrument based on this signal are often used. There is. Among these, especially for instruments that require predetermined arithmetic processing when converting the output of the measured object into the instrument drive output, there is a conversion section that digitizes the output signal from the measured object, and a conversion section that The device includes a drive processing unit that generates a predetermined drive output in response to a digital signal input from the device, and a display unit that operates the pointer in response to the drive output.

Regarding the above conversion section, especially in the case of a frequency output that emits a pulse signal every time the measurement object changes by a predetermined value, such as a speedometer, it is composed of an F-V conversion section and an A-D conversion section, and the F-V The conversion section often uses a so-called integration circuit that combines a capacitor and a resistor to smooth the pulse signal and convert it into a voltage value.The A-D conversion section converts the voltage value into a digital value corresponding to the voltage value, and converts this digital value into a digital value. is output to the next drive processing section.

(Problem to be solved by the invention) F-V in the above-mentioned indicating instrument using digital processing
The converter is composed of a capacitor and a resistor, and since the accuracy of the capacitor varies greatly, it is often seen that the actual output value of the F-V converter differs from the designed output value.

Therefore, we proposed a method for direct digital conversion without performing F-V conversion and A-D conversion (Japanese Patent Application No. 1-1370
No. 79) This adds a constant value to the operand value every time a pulse (C) is emitted from the object to be measured, and adds a constant value to the operand value at a constant period that is emitted regardless of the pulse signal. It performs the process of adding the corresponding subtracted value or the subtracted value that is a constant value, and outputs the processing result (operand value) to the conversion section described above, and the output of this conversion section is such that the addition value and subtraction value are balanced. Since the conversion unit output (digital value) is approximately stable at a value that can be taken, the output of the converter (digital value) corresponds to the generation frequency of the pulse ( ) of the object to be measured.

In this frequency digital conversion means, the width of the pulse signal period from the object to be measured is wide, and various inconveniences will occur if the same processing is performed on low frequency input and high frequency input. For example, when the pulse signal period becomes longer, ripples occur in the output of the converter which is the result of arithmetic processing, and the pointer shakes due to this ripple. Regarding this guideline fluctuation, next is 16 bits.
- (hereinafter expressed as 0000 to FFFF) will be specifically explained using an example of arithmetic processing.

The setting conditions are: V(n): Operand value at any time ■ Subtraction processing cycle T = 1 + n5ec ■ Value added per 1 input pulse C, = 0800 ■
The output is the upper 8 bits of the calculation result V(n).

and the input pulse period is 10m sec and 100m
If the case of sec is plotted as a graph, it will be as shown in FIG.

f! The initial value is 1" (000J).

As shown in Figure 6 (a), the input pulse period is 10m5e.
In the case of C, the converter output increases every 10m5ec,
Since the pointer cannot follow this periodic variation, the pointer does not actually shake. On the other hand, the input pulse period as shown in Figure 6 (υ) is 100 m in the case of 100 m set.
The output of the converter increases every time the converter outputs the indicator, and the pointer of the indicator is driven in response to the output of the converter, so naturally the pointer oscillates.

Therefore, as a means to prevent the pointer from shaking during low frequency input,
Possible methods include reducing the addition value and performing subtraction slowly, and dividing the addition into parts to prevent protrusions during addition. However, when the above means is adopted, a problem occurs when a high frequency pulse signal is input. That is, in the former case, if the input pulse period is short, sufficient subtraction is not performed and the converter output cannot be stabilized, and in the latter case, the division and addition will not be completed within the input pulse period. This means that the desired converter output cannot be obtained.

(Means for Solving the Problems) The present invention has been made in view of the above-mentioned problems in the means for directly converting the period number input into digital data and using it as a driving reference for a meter, and has proposed an improvement thereof.

In the driving method of the indicating instrument according to the present invention, a pulse equal signal is emitted every time the object to be measured changes by a predetermined amount, and a constant value is added to the operand value of the pulse signal input word, and a predetermined value is subtracted at regular intervals. , a driving method for an indicating instrument that determines the index of the indicating instrument based on the result of a calculation process, comprising a determining section that compares the input period of the pulse signal with the set period; This method is characterized in that the arithmetic processing cycle, such as the division and addition cycle of a constant value or the subtraction cycle of a predetermined value, is changed depending on the determination result.

(Function) Pulses from the object to be measured (as a countermeasure against low frequency input in No. 3, a constant value is divided and added to the operand value every time a pulse signal is input, and a predetermined value is subtracted at regular intervals. When you do it,
The numerical value of the calculation result corresponds to the frequency of the input pulse signal, and even if the period of the input pulse signal is particularly long, the constant value itself is divided and added, so that no standout value occurs in the calculated processing result. In addition, for high-frequency inputs for which the judgment section determines that the period of the input pulse signal is greater than a predetermined setting period, the period of division and addition is shortened, constant value addition corresponding to the input pulse signal is performed, and the calculation is performed. The result corresponds to the input frequency of the input pulse signal.

As a countermeasure against low frequency input, the processing result is stabilized even with low frequency input by reducing the addition value, lengthening the subtraction period accordingly, and performing the subtraction slowly.

Furthermore, when inputting a high frequency, 2
! By shortening the iJi computation period, the computed processing results at the time of high frequency input are also stable, and the computed processing results corresponding to the input cabling signal frequency can be obtained.

(Example) Next, embodiments of the present invention will be described based on the drawings.

Figure 1 is a block diagram of the entire instrument, Figure 2 is the details of the converter, Figure 3 is a graph showing the output of the division constant value, and Figure 4 is another example of the converter. In the block diagram, the fifth
The figure is an output graph of the converter when the subtraction period is changed in the case of the embodiment of FIG. 4.

The embodiment shown in FIGS. 1 to 3 will be described below.

The overall configuration of the indicating instrument consists of a converting section 1. Consisting of a drive processing section 2 and a display section 3, the conversion section 1 outputs a digital value corresponding to the pulse frequency when a pulse (No. 8) is input according to the operation of the object to be measured. The drive processing section 2 includes a ROM section 21.D-A conversion section 22
．． It consists of a drive output section 23, and the ROM section 21 stores a digital output corresponding to the output signal (digital numerical value) of the converting section 1 described above, and upon receiving the output of the converting section, outputs the memorized digital numerical value, The next DA converter 22 converts the digital numerical signal into an analog signal and sends it to the drive output unit 23 . The drive output section 23 outputs a drive current for driving the pointer.

In addition, the display section 3 consists of a pointer 2 display board, a drive coil, etc.
Drive from the drive output section 23 described above! [! It can be operated with 11 current.

The details of the converter 1 are as shown in FIG.
．． Timing pulse generator 12. Latch circuit 13, subtraction value setter 141 and addition Pi? 142 and the operation ViJ14. It consists of an adder 151 and a judger 16. When the constant setter 11 receives the input of the pulse signal n from the object to be measured, it divides the preset constant value into a predetermined number, and sequentially outputs the divided constant values in synchronization with the signal from the timing pulse generator 12. , is sent to the adder 15. The timing pulse generator 12 is outputted to all the circuits in the conversion section], and each circuit operates according to the reference of this timing pulse.
c), calculation timing output section B (period 1 + m5ae)
, an addition timing output section C+ (period: 4 m5ec), and addition timing output section Cm (period: 1 mffee). The latch circuit 13 latches the converter output numerical value and outputs it to the arithmetic unit 14. The arithmetic unit 14 uses an adder 142 to add a subtraction value determined by a subtraction value setter 141 to the numerical value output from the latch circuit 13, and outputs the result to an adder 15. Adder 1
5 adds the respective output values of the constant setter II and the adder 141 to obtain an output numerical value (processing result) of the converter 1. [Judgment unit] 6 receives the input of a pulse signal and counts until the next pulse (S) is input, and when it exceeds a predetermined count number (set cycle), it determines that it is a low frequency input, and the judgment result Timing pulse generator 12 by
The addition timing output section C, , C, is selected.

Next, the above operation will be explained.

First, a case where there is no output from the constant setter 11 will be explained.

Calculation timing output section B of timing pulse generator 12
The output is a timing pulse (C) with a constant period, which is output to each circuit (excluding constant setting Vij11), and each circuit performs a predetermined calculation process in each circuit in synchronization with this pulse signal. When this timing pulse generator is output, the operand value held in the latch circuit 13 is output to the subtraction value setter 141 and adder 142 in the operation 114. This is a circuit that converts a value corresponding to a certain percentage of the calculated operand value into a negative value and sets it as a subtraction value, and the adder 142 adds this subtraction value and the operand value and outputs it to the addition Pg 15. The adder 15 is a circuit that adds the operand output from the adder 142 of the arithmetic unit 14 and the constant output from the constant setter 11. However, since there is no output from the constant setting Vii 11 at this time, the adder 15 As the output, the operand value of the adder 142 is output as is.This output is output as a new operand value to the latch @ approximately 13, and this operand value is sent to the ROM section 6 shown in FIG. Output to.

Therefore, if the above process is repeated every time the timing pulse generator from the calculation timing output unit B is output (every 1mlce), the operand value will gradually decrease.

Next, the case where there is a numerical output from the constant setter 11, that is, when the pulse signal a is input to the converter 1 from the object to be measured, will be explained.

First, when the arithmetic processing result in the determiner 16 is smaller than the set value, when the pulse signal from the object to be measured is input to the constant setter 11 in the converter 1, the divided sum value is sent from the constant setter 11 to the adder 15. (See FIG. 3(A)) This divided addition value and the operand value output from the arithmetic unit 14 are added together. In this addition process, addition is performed a predetermined number of times using the period (long-term addition period) of output pulse No. 41 (4m5ec) from the addition timing output unit CI. Therefore, when the pulse (No. 3) is input to the constant setter 11, the output value of the arithmetic unit 14 and the output value of the constant setter 11 are added in addition 1115 with a long-term addition cycle, and during that period, the output value of the constant setter 11 is shorter than the cycle of this addition. The subtraction processing described above is performed. Therefore, the output of the converter 1 becomes a numerical value in which the added value and the subtracted value are balanced.

Next, when the period of the human pulse signal a becomes shorter than a preset period in the determiner 16 (when the count value is less than a predetermined value), specifically, at least the output if signal period of the addition timing output section C1. Then, before the pulse (No. 3 a) reaches the range where it is assumed that the divisional addition will not be completed within the input cycle, the determination result from the determiner 16 is sent to the timing pulse generator 12, and the addition timing output is sent to the addition timing generation section. From the signal from C1 (period: 4 m5ec), the output signal of addition timing generator C (period: 1 m5ec)
5ec). Therefore, the pulse signal a
The constant value corresponding to one input of is always added (see Figure 3 (b)). Therefore, rather than adding all the constant values in one cycle, if you divide the constant values and add them, Since no protruding value occurs in the low frequency input, and since the period of division and addition is switched and changed depending on the period of the input pulse equal sign, even in division and addition, it is always possible to complete the calculation by the time the next pulse signal a is input. A constant value is added corresponding to the input pulse.

Next, the second embodiment (ζ) shown in FIGS. 4 and 5 will be explained.

The second embodiment does not employ the above-mentioned division and addition, but instead handles a wide range of low-frequency inputs and high-frequency inputs by switching the subtraction processing cycle.

In this embodiment, the output of the constant setter 11 is not a divided constant output, but a constant value output that does not cause the pointer to shake, and the timing pulse generator 12 is used to generate a reference pulse as shown in FIG. part Δ, calculation timing output part B+ (period 4 m5ec), calculation timing output part Bt (period 1w1ce), and addition timing output part C (period 1 m5ec), and determiner 16
The calculation timing output units B, , B are switched based on the determination result.

The operation of the above configuration will be explained.

The calculation method is similar to the above-described division and addition embodiment, and a constant value is added to the adder 15 each time the pulse signal a is input, and a predetermined value is added each time there is an output signal from the calculation timing output section B1 or B2. The subtraction is performed. In this subtraction, when the determiner 16 determines that the input is a low frequency input, &JjJ1
The calculation timing output part B, which is a cycle, is output, and calculation processing is performed according to the timing of the output signal of the output part B. When the determiner 16 determines that it is a high frequency input, it switches to the calculation timing output section B2, which has a short period, and performs calculation processing.

Therefore, if low-frequency input is processed at the same calculation timing as high-frequency input processing, the converter output will be unstable as shown in Figure 5 (a), but by slowing down the subtraction timing, As shown, a stable converter output can be obtained.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can be changed as long as it determines whether the period of the human pulse signal is longer or shorter than the set period, and changes the arithmetic processing period based on the determination result. may be applied to a divided addition cycle, a subtraction cycle, or a combination of both.

(Effects of the Invention) As described above, when the present invention receives the display pulse No. 43 output from the object to be measured, which is a frequency input, it adds a constant value to the input radio wave calculation value, and also adds a predetermined value at a constant period. In the method of obtaining the output value corresponding to the frequency input by subtraction and driving the meter, the above addition is divided into additions to prevent the pointer of the indicator 31 from shaking due to fluctuations in the output value when the pulse signal input is at a low frequency. This is to prevent the pointer from wobbling due to low frequency input, etc., by adjusting the subtraction period or by shifting the subtraction period to a longer period, and to cope with high frequency input by setting each arithmetic processing period to a short period.

[Brief explanation of drawings]

Fig. 1 is an overall block diagram of the instrument implementing the present invention, Fig. 2 is a detailed block diagram of the converter, and Fig. 3 is a graph showing the output of the constant setter, and (a) shows the low frequency input. (B)
Indicates high frequency input. FIG. 4 is a partial block diagram of the converting section showing the second embodiment, and FIG. 5 is a graph showing the converting section output at low frequency input when implementing the method shown in FIG. , (+=) indicates the case where the present invention is used, and Figure 6 is a graph showing the converter output when the present invention is not implemented. (,?) indicates the high frequency input, and (t+) indicates the low frequency input. shows. (2) is the converter 11 (the constant setter 12 is the timing pulse generation type 13 is the latch circuit 14 is the calculation 2B!411.f The subtraction value setter 142 is the adder 15 is the adder] 6; the determiner 2 is the rqA! Ii!J processing section 21+, ROM section 22, D-A conversion section 23, drive output section 3, display section Fig. 3, Fig. 4, Fig. 2

Claims (1)

[Claims] (1) A pulse signal is emitted every time the object to be measured changes by a predetermined amount, and a constant value is added to the operand value every time this pulse signal is input, and a predetermined value is subtracted at regular intervals, and based on the calculated processing result. The method for driving an indicating instrument that determines the index of the indicating instrument by determining the index of the indicating instrument includes a determining section that compares the length of the input period of the pulse signal and the set period, and divides the constant value based on the determination result of the determining section. 1. A method for driving an indicating instrument, characterized by changing an arithmetic processing cycle such as an addition cycle or a predetermined value subtraction cycle.