JPH03113379A - Driving method for indicating instrument - Google Patents
Driving method for indicating instrumentInfo
- Publication number
- JPH03113379A JPH03113379A JP25268689A JP25268689A JPH03113379A JP H03113379 A JPH03113379 A JP H03113379A JP 25268689 A JP25268689 A JP 25268689A JP 25268689 A JP25268689 A JP 25268689A JP H03113379 A JPH03113379 A JP H03113379A
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- Prior art keywords
- value
- period
- signal
- output
- subtraction
- Prior art date
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- 238000000034 method Methods 0.000 title claims description 13
- 238000006243 chemical reaction Methods 0.000 abstract description 19
- 238000005259 measurement Methods 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
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Abstract
Description
【発明の詳細な説明】 (産業上の利用分W> 本発明は指示計器の駆動方法に関するものである。[Detailed description of the invention] (Industrial usage W> The present invention relates to a method for driving an indicating instrument.
(従来の技術)
指示計器において被測定対象からの表示用出力を適宜な
電気信号(周波数、電圧値等)に変換し、この信号に基
づいて指示計器の指針を動作せしめるものが多用されて
いる。この内特に被測定対象の出力を計器駆動出力に変
換するに際して、所定の演算処理を必要とする針留に於
ては、被測定対象からの出力48号のデジタル化をなす
変換部と、変換部からのデジタル(ス号入力に応じて所
定の駆動出力をなす駆動処理部と、駆動出力を受けて指
針を動作せしめる表示部を備えてなる。(Prior art) Indicating instruments that convert the display output from the object to be measured into an appropriate electrical signal (frequency, voltage value, etc.) and operate the pointer of the indicating instrument based on this signal are often used. . Among these, especially in needle holders that require predetermined calculation processing when converting the output of the object to be measured into the meter drive output, there is a conversion section that digitizes the output No. 48 from the object to be measured, and a conversion section that digitizes the output No. 48 from the object to be measured It is equipped with a drive processing section that generates a predetermined drive output in response to a digital signal input from the section, and a display section that receives the drive output and operates the pointer.
前記の変換部については、特にスピードメークのように
測定対象が所定量変化する毎にパルス信号を発する周波
数出力の場合は、F−V変換部及びA−D変換部から構
成され、F−V変換部はコンデンサ及び抵抗を組み合わ
せパルス信号を平滑して電圧値に変換する所謂積分回路
が多用されており、Δ−D変換部は前記の電圧値に対応
するデジタル数値に変換し、このデジタル数値を次の駆
動処理部に出力しているものである。Regarding the above-mentioned conversion section, especially in the case of a frequency output that emits a pulse signal every time the measurement target changes by a predetermined amount, such as speed making, it is composed of an F-V conversion section and an A-D conversion section, and the F-V The conversion section often uses a so-called integration circuit that combines a capacitor and a resistor to smooth a pulse signal and convert it into a voltage value, and the Δ-D conversion section converts the voltage value into a digital value corresponding to the voltage value. is output to the next drive processing section.
(発明が解決しようとする課題)
前述したデジタル処理を用いる指示計器におけるF−V
変換部は、コンデンサと抵抗で構成され、特にコンデン
サの精度のバラツキが大きいので実際のF−V変換部の
出力数値と設計で求めた出力値とが異なる場合が屡々見
受けられる。(Problem to be solved by the invention) F-V in the above-mentioned indicating instrument using digital processing
The converter is composed of a capacitor and a resistor, and since the accuracy of the capacitor varies greatly, it is often seen that the actual output value of the F-V converter differs from the designed output value.
そこでF−V変換及びA−D変換を行わずに、直接デジ
タル変換する手段を先に提案した(特願平1−1376
79号) これは被測定対象からパルス信号が発せら
れる毎に被演算値に定数値を加算し、且つパルス信号と
は無関係に発せられる一定周期毎に前記被演算値の一定
の割合に相当する減算値又は一定値である減算値を加算
する処理を行い、処理結果(被演算値)を前記の変換部
出力をするもので、この変換部出力は加算値と減算値と
の釣り合いがとれる数値に略安定するので変換部出力(
デジタル数値)は、被測定対象のパルス43号の発生周
波数と対応することになるものである。Therefore, we proposed a method for direct digital conversion without performing F-V conversion and A-D conversion (Japanese Patent Application No. 1-1376).
No. 79) This means that a constant value is added to the operand value each time a pulse signal is emitted from the object to be measured, and it corresponds to a certain percentage of the operand value for each fixed period that is emitted regardless of the pulse signal. It performs processing to add a subtracted value or a constant subtracted value, and outputs the processing result (operand value) to the conversion section described above, and the output of this conversion section is a numerical value that balances the addition value and subtraction value. Since the converter output (
The digital numerical value) corresponds to the generation frequency of pulse No. 43 to be measured.
この周波数のデジタル変換手段に在っては、被測定対象
からのパルス信号周期の幅が広く、低周波入力も高周波
入力も同様の処理を行うと、種々の不都合が生ずる。例
えばパルス信号周期が長くなると演算処理結果となる変
換部出力にリップルが発生し、このリップルに基づく指
針ブレが生ずる。この指針ブレについて次に16ビツト
(以下0000〜FFFFで表示する)での演算処理例
を用いて具体的に説明する。In this frequency digital conversion means, the width of the pulse signal period from the object to be measured is wide, and various inconveniences will occur if the same processing is performed on low frequency input and high frequency input. For example, when the pulse signal period becomes longer, ripples occur in the output of the converter which is the result of arithmetic processing, and the pointer shakes due to this ripple. Next, this pointer deviation will be specifically explained using an example of arithmetic processing using 16 bits (hereinafter expressed as 0000 to FFFF).
設定条件を、
VC?L)
■減算処理式 V (n +1 ) =” (” )
21〒V(n)i任意時における被演算値
■減算処理周期 T==1msec
■入力1パルス当たり加算する値 C1= 0800■
出力は演算結果V(n)の上位8 bitとする。Setting conditions, VC? L) ■Subtraction processing formula V (n +1) =” (”)
21〒V(n)i Operand value at any time ■ Subtraction processing cycle T = = 1 msec ■ Value added per 1 input pulse C1 = 0800 ■
The output is the upper 8 bits of the calculation result V(n).
と定め、入力パルス周期を10tn seeとIQQm
3eeの場合をグラフにすると、第5図に示す通りと
なる。and the input pulse period is 10tn see and IQQm
If the case of 3ee is plotted as a graph, it will be as shown in FIG.
I11シ初期値はr 0OOOJとする。The initial value of I11 is r0OOOJ.
第4図 (イ)に示すように入力パルス周期が10ff
l ff1eeの場合は変換部出力は10m5ee毎に
突出するが、指針がこの周期変動に追従できないため、
実際には指針ブレが生じない。これに対して第4図(+
ff)に示すような入力パルス周期は100m sec
の場合100m see毎変換部出力が突出し、指示計
器の指針はこの変換部出力に対応して駆動せしめられる
ので、当然指針ブレが生ずることになる。As shown in Figure 4 (a), the input pulse period is 10ff.
In the case of lff1ee, the converter output jumps every 10m5ee, but since the pointer cannot follow this periodic fluctuation,
In reality, the guideline does not shake. In contrast, Fig. 4 (+
The input pulse period as shown in ff) is 100 m sec
In this case, the output of the converter increases every 100 msee, and the pointer of the indicator is driven in accordance with the output of the converter, which naturally causes the pointer to oscillate.
そこで低周波入力時の指針振れを防止する手段として、
加算値を小さくシ、且つ減算周期を大きくして減算を緩
やかに行うことが考えられる。しかし前記手段を採用す
ると、入力パルス信号の周期が短い高周波入力時に充分
な減算が行われずに変換部出力の安定が得られないと云
う不都合が生じ、また減算周期をパルス信号の入力周波
数に対応して変更すると、演算した処理結果とパルス信
号の入力周波数との間に連続した一定の関数関係が成立
しないと云う不都合が生ずる。Therefore, as a means to prevent the pointer from shaking during low frequency input,
It is conceivable to perform subtraction slowly by making the addition value small and the subtraction period large. However, when the above-mentioned method is adopted, there is a problem that when a high frequency input pulse signal with a short period is input, sufficient subtraction is not performed and the output of the converter cannot be stabilized. If this is changed, a problem arises in that a continuous constant functional relationship is not established between the calculated processing result and the input frequency of the pulse signal.
(課題を解決するための手段)
本発明は周期数入力を直接デジタル変換して計器の駆動
基準とする手段における前記の問題点を鑑み、これを改
善する提案をしたものである。(Means for Solving the Problems) The present invention has been made in view of the above-mentioned problems in the means for directly converting the period number input into digital data and using it as a driving reference for a meter, and has proposed an improvement thereof.
本発明に係る指示計器の駆動方法は、被測定対象が所定
旦変化する毎にパルス信号が発せられ、パルス信号入力
毎被演算値に定数値を加算すると共に、所定周期を以て
所定値を減算し、演算した処理結果に基づいて指示計器
の指度を決定する指示計器の駆動方法に於て、減算周期
を変更可能にすると共に、減算周期の変更に対応して加
算値に前記減算周期に反比例して変更してなることを特
徴とするものである。In the driving method of the indicating instrument according to the present invention, a pulse signal is emitted every time the object to be measured changes by a predetermined time, a constant value is added to the operand value every time the pulse signal is input, and a predetermined value is subtracted at a predetermined period. In the driving method of the indicating instrument that determines the index of the indicating instrument based on the calculated processing result, the subtraction cycle can be changed, and in response to the change in the subtraction cycle, the addition value is inversely proportional to the subtraction cycle. It is characterized in that it is made by changing.
(作 用)
被測定対象からのパルス信号の低周波入力対策として、
パルスイコ号が入力する毎に被演算値に対しての定数値
の加算を行い、所定周期で所定値の減算を行う際に、減
算周期を長くし減算を緩やかに行うと共に、加算値も減
算周期に反比例して変更すると、減算周期を変更しても
、演算した処理結果と入力パルス信号周波数との関数関
係に何等の変化も生じない。従って入力パルス信号が低
周波入力となっても高周波入力となっても、その演算結
果は安定したものとなる。(Function) As a countermeasure against low frequency input of pulse signals from the object to be measured,
Every time a pulse equal sign is input, a constant value is added to the operand value, and when subtracting a predetermined value at a predetermined period, the subtraction period is lengthened and the subtraction is performed slowly, and the addition value also changes at the subtraction period. If it is changed in inverse proportion to , even if the subtraction period is changed, no change occurs in the functional relationship between the calculated processing result and the input pulse signal frequency. Therefore, whether the input pulse signal is a low frequency input or a high frequency input, the calculation result will be stable.
(実施例) 次に本発明の実施例を図面に基づいて説明する。(Example) Next, embodiments of the present invention will be described based on the drawings.
第1図は計器全体のブロック図であり、第2図は変換部
の詳細で第3図は低周波入力時の変換部の出力を示すグ
ラフで、(イ)は本発明の実施前で(+7)は本発明の
実施した状態のものを示すものである。FIG. 1 is a block diagram of the entire instrument, FIG. 2 is a detailed diagram of the converter, and FIG. 3 is a graph showing the output of the converter when a low frequency input is applied. +7) shows the state in which the present invention is implemented.
指示計器の全体の構成は、変換部1.駆動処理部2及び
表示部3よりなり、変換部1は被測定対象の動作に応じ
て発生するパルス信号が入力すると、パルス周波数に応
じたデジタル数値を出力するもので、その詳細は後述す
る。駆動処理部2はItOM部21.D−A変換部22
.駆動出力部23カラなり、ROM部21は前記した変
換部1の出力信号(デジタル数値)と対応するデジタル
出力をメモリしたもので、前記変換部出力を受けるとメ
モリしたデジタル数値の出力をなし、次のD−A変換部
22で前記デジタル数値信号をD−A変換し、駆動出力
部23に送る。駆動出力部23では指針を駆動せしめる
ための駆動電流を出力するものである。The overall configuration of the indicating instrument consists of a converting section 1. The conversion section 1 is composed of a drive processing section 2 and a display section 3, and when a pulse signal generated according to the operation of the object to be measured is input, the conversion section 1 outputs a digital numerical value according to the pulse frequency, the details of which will be described later. The drive processing section 2 includes an ItOM section 21. D-A converter 22
.. The drive output section 23 is color, and the ROM section 21 stores a digital output corresponding to the output signal (digital numerical value) of the converting section 1 described above, and upon receiving the output of the converting section, outputs the memorized digital numerical value. The next DA converter 22 converts the digital numerical signal into an analog signal and sends it to the drive output unit 23 . The drive output section 23 outputs a drive current for driving the pointer.
また表示部3は指針1表示板、駆動コイル等からなり、
前記した駆動出力部23からの駆動電流で動作せしめら
れるものである。In addition, the display section 3 consists of a pointer 1 display board, a drive coil, etc.
It is operated by the drive current from the drive output section 23 described above.
変換部1の詳細は第2図に示す通りで、定数設定器11
.タイミングパルス発生器12.ラッチ回路13、減算
値設定器141と加算器142とで構成される演算器1
4.加算器15.切換器16よりなる。定数設定111
は定数発生部111と乗算部目2からなり、定数発生部
111は被測定対象からのパルス信号αの入力を受ける
と、予め設定した定数値を所定数に分割し、タイミング
パルス発生器12からの演算処理43号と同期して分割
定数値を順次乗算部112に出力し、乗算部112は後
述する分周部122からの分周比Nを前記分割定数値に
乗じてその乗算結果である分割加算値を、加算器15に
送り込むものである。タイミングパルス発生器12は基
準パルス発生部1212分周部122.処理パルス発生
部123よりなり、基準パルス発生部121は回路全体
の基準パルスを発生し、分局部122は前記基準パルス
を17Hに分周するもので、分局の程度は後述の切換器
16の指示による。また処理パルス発生部123は変換
部1内の総ての回路に演算処理信号を出力するもので、
各回路はこの演算処理信号の基準毎に動作するものであ
る。ラッチ回路13は変換部出力数値をラッチするもの
で、演算1!!J14に出力する。演算器14はラッチ
回!@13からの出力数値を減算値設定器141で定め
た減算値の加算を加算VB142で行い、加算器15に
出力する。加算器15は定数設定器11と加算器141
の各出力値の加算を行い、変換部1の出力数値とするも
のである。切換器16は演算結果又はパルス信号入力或
いは両者の入力を受け、分周部】22に切換信号を発す
るもので、入力パルス信号が高周波入力と判定した場合
は、分局比が大きくなりg算周期が短くなるように指示
するものである。The details of the converter 1 are as shown in FIG.
.. Timing pulse generator 12. Arithmetic unit 1 consisting of latch circuit 13, subtraction value setter 141 and adder 142
4. Adder 15. It consists of a switching device 16. Constant setting 111
consists of a constant generator 111 and a multiplier 2. When the constant generator 111 receives the input of the pulse signal α from the object to be measured, it divides a preset constant value into a predetermined number and outputs the signal from the timing pulse generator 12. The division constant values are sequentially outputted to the multiplication unit 112 in synchronization with calculation process No. 43, and the multiplication unit 112 multiplies the division constant value by a frequency division ratio N from the frequency division unit 122, which will be described later, to obtain the multiplication result. The divided and added values are sent to the adder 15. The timing pulse generator 12 includes a reference pulse generator 1212, a frequency divider 122. Consisting of a processing pulse generator 123, the reference pulse generator 121 generates a reference pulse for the entire circuit, and the division part 122 divides the frequency of the reference pulse into 17H. by. Further, the processing pulse generator 123 outputs arithmetic processing signals to all the circuits in the converter 1.
Each circuit operates on the basis of this arithmetic processing signal. The latch circuit 13 latches the converter output numerical value, and operates 1! ! Output to J14. Arithmetic unit 14 is latched! An addition VB 142 adds a subtraction value determined by a subtraction value setter 141 to the output numerical value from @13, and outputs the result to an adder 15. Adder 15 includes constant setter 11 and adder 141
The output values of the converter 1 are obtained by adding the respective output values. The switch 16 receives the calculation result or the pulse signal input, or both, and issues a switching signal to the frequency dividing section 22. If the input pulse signal is determined to be a high frequency input, the division ratio becomes larger and the g calculation period increases. This is an instruction to make the length shorter.
次に前記の動作を説明する。Next, the above operation will be explained.
まず定数設定器11の出力がない場合について説明する
。First, a case where there is no output from the constant setter 11 will be explained.
タイミングパルス発生器12の演算処理信号を各回路(
但し定数設定器11は除く)へ出力し、各回路はこの処
理(1号に同期して各回路の所定の演算処理を行うもの
である。この処理信号が出力されると、ラッチ回路13
に保持されていた被演算値が演算器14内の減算値設定
器141及び加算VB142へ出力される。減算値設定
器141では、出力された被演算値の一定の割合に相当
する値を負の値にして減算値として設定する回路であり
、加算器142ではこの減算値と被演算値を加算して加
算@815へ出力する。加算器15は演算器14の加算
器142から出力された被演算値と定数設定器11が出
力する定数を加算する回路であるが、このときの定数設
定器11からの出力がないので加算器15の出力は前記
加算器142の被演算値がそのまま出力される。この出
力は前記ラッチ回路13に新たな被演算値として出力さ
れると共に、この被演算値を第1図に示したROM部6
へ出力する。The arithmetic processing signal of the timing pulse generator 12 is transmitted to each circuit (
However, the constant setter 11 is excluded), and each circuit performs this process (predetermined arithmetic processing of each circuit in synchronization with No. 1). When this processed signal is output, the latch circuit 13
The operand value held in is output to the subtraction value setter 141 and the addition VB 142 in the arithmetic unit 14. The subtraction value setter 141 is a circuit that sets a value corresponding to a certain percentage of the output operand value as a negative value as a subtraction value, and the adder 142 adds this subtraction value and the operand value. and output to addition@815. The adder 15 is a circuit that adds the operand output from the adder 142 of the arithmetic unit 14 and the constant output from the constant setter 11, but since there is no output from the constant setter 11 at this time, the adder 15, the operand value of the adder 142 is output as is. This output is output to the latch circuit 13 as a new operand value, and this operand value is stored in the ROM section 6 shown in FIG.
Output to.
従って、タイミングパルス発生Pj12からの処理信号
が出力される毎に前記処理を繰り返すと、被演算値は徐
々に減少する値となる。Therefore, if the above processing is repeated every time the processed signal from the timing pulse generation Pj12 is output, the operand value will become a value that gradually decreases.
次に定数設定器11から数値出力がある場合即ち被測定
対象から変換部1にパルス信号aが入力したときについ
て説明する。Next, the case where there is a numerical output from the constant setter 11, that is, the case where the pulse signal a is input to the converter 1 from the object to be measured will be explained.
変換部1内の定数設定器11に被測定対象からのパルス
信号が入力すると、定数設定器11の定数発生部111
から分割定数値が乗算部112に入力し、所定の演算(
後述)が施され、その演算結果(分割加算値)が加算器
15へ出力され、この分割加算イαと演算器14から出
力される被演算値とが加算されることになる。従ってパ
ルス信号が定数設定511に入力すると、処理信号の周
期を以て加算器15で演算器14の出力値と定数設定器
11の出力値の加算がなされ、同時に前記した減算処理
が行われる。When a pulse signal from the object to be measured is input to the constant setter 11 in the converter 1, the constant generator 111 of the constant setter 11
The division constant value is input to the multiplier 112 from , and a predetermined calculation (
(described later) is performed, and the result of the operation (divided addition value) is output to the adder 15, and this divided addition α and the operand value output from the arithmetic unit 14 are added together. Therefore, when a pulse signal is input to the constant setting unit 511, the adder 15 adds the output value of the arithmetic unit 14 and the output value of the constant setting unit 11 at the cycle of the processed signal, and simultaneously performs the above-described subtraction process.
このため変換部1の出力は加算値と減算値とが釣り合う
数値となる。Therefore, the output of the converter 1 becomes a numerical value in which the added value and the subtracted value are balanced.
次に切換器16において演算した処理結果又は入力パル
ス信号の周期が予め設定した値より大ぎく、なった場合
や、逆に小さくなった場合に、切換器16よりタイミン
グパルス発生部12に切換信号を送り、分周部122の
分周比率を変更させるものである。即ち低周波入力と判
定した場合は分局比を大きくして処理パルス発生部12
3からの演算処理信号周期を長くし、減算処理を緩やか
に行うものである。このとき分局部122より定数発生
illの乗算部112に分周比の逆数信号を送り、乗算
部112で定数発生部111からの分割定数値に分局比
の逆数を乗じて演算処理信号周期が長くなった分少ない
数値とした分割加算値を加算器15に出力するものであ
る。また逆に切換器16が高周波入力と判定した場合は
、分局比を小さくシ、演算処理信号周期を短くし、減算
処理を素早く行い、前記周期を短くしたのに反比例させ
て分割加算値を大きくするものである。Next, if the processing result calculated by the switch 16 or the cycle of the input pulse signal becomes too large or smaller than a preset value, the switch 16 sends a switching signal to the timing pulse generator 12. is sent to change the frequency division ratio of the frequency divider 122. In other words, if it is determined that the input is a low frequency input, the division ratio is increased and the processing pulse generator 12
The period of the arithmetic processing signal from No. 3 is lengthened, and the subtraction processing is performed slowly. At this time, the division section 122 sends a reciprocal signal of the division ratio to the multiplication section 112 of the constant generation ill, and the multiplication section 112 multiplies the division constant value from the constant generation section 111 by the reciprocal of the division ratio to increase the period of the arithmetic processing signal. The divided and added value is outputted to the adder 15 with a smaller numerical value corresponding to the difference. Conversely, if the switch 16 determines that it is a high frequency input, the division ratio is reduced, the arithmetic processing signal period is shortened, and subtraction processing is quickly performed, and the division addition value is increased in inverse proportion to the shortened period. It is something to do.
従って特に指針ブレが生じ易い低周波入力の場合は、第
3図(ロ)に示すように減算周期を長くすると共に加算
値を所定の処理を以て減少させると、無処置の場合の同
図(イ)に比して変換部の出力は安定し、計器の指針ブ
レが生じないものである。Therefore, in the case of low-frequency input that is particularly prone to pointer wobbling, it is possible to lengthen the subtraction cycle and reduce the added value through a predetermined process, as shown in Figure 3 (B), compared to the same figure (I) in the case of no treatment. ), the output of the converter is more stable and the meter pointer does not shake.
またバルスイコ号の高周波入力に対しても充分対応でき
、而も演算結果たる変換部出力は入力パルス信号の周波
数と対応することになるものである。Moreover, it can sufficiently cope with the high frequency input of the Valsico signal, and the output of the conversion section, which is the calculation result, corresponds to the frequency of the input pulse signal.
尚本発明は前記実施例に限定されるものでなく、定数設
定器11の出力を特に分割加算値の出力とせずにパルス
信号入力に際して所定の加算値を一回出力するものでも
良い。It should be noted that the present invention is not limited to the above-mentioned embodiment, and the output of the constant setter 11 may not be a divided addition value, but a predetermined addition value may be output once upon input of a pulse signal.
(発明の効果)
本発明は以上のように周波数入力となる被測定対象から
の表示用パルス信号出力を受けると、その入力倍波演算
値に定数値を加算し、且つ一定周期を以て所定値を減算
することで周波数入力と対応する出力数値を得て計器を
駆動せしめる手法に於て、減算周期を変更すると共に、
減算周期の変更に対応して加算値も変更したもので、パ
ルス信号の低周波入力にもまた高周波入力にも対応でき
るようにしたものである。(Effects of the Invention) As described above, when the present invention receives a display pulse signal output from an object to be measured, which is a frequency input, a constant value is added to the input harmonic calculation value, and a predetermined value is added at a constant period. In the method of obtaining the output value corresponding to the frequency input by subtraction and driving the instrument, the subtraction period is changed and
The addition value is changed in accordance with the change in the subtraction period, so that it can correspond to both low-frequency input and high-frequency input of pulse signals.
第1図は本発明を実施した計器の全体のブロック図、第
2図は変換部のブロック詳細図、第3図は低周波入力時
の変換部の出力を示したグラフで、(−C)は減算周期
を変更しない場合、(的は減算周期を長くした場合を示
す。
1は変換部
lは定数設定器
11は定数発生部
12は乗算部
2ばタイミングパルス発生器
21は基準パルス発生部
122ば分周部
123は処理パルス発生部
13はラッチ回路
14は演算器
141は減算値設定器
142は加算器
15は加算器
16は切換器
2は駆動処理部
21はROM部
22はD−A変換部
23は駆動出力部
3は表示部Fig. 1 is an overall block diagram of the instrument implementing the present invention, Fig. 2 is a detailed block diagram of the converter, and Fig. 3 is a graph showing the output of the converter when low frequency input is performed. 1 indicates the case where the subtraction period is not changed, (the mark indicates the case where the subtraction period is lengthened. 1 indicates the conversion section l, the constant setter 11, the constant generation section 12, the multiplication section 2, and the timing pulse generator 21, the reference pulse generation section. 122, the frequency divider 123, the processing pulse generator 13, the latch circuit 14, the arithmetic unit 141, the subtraction value setter 142, the adder 15, the adder 16, the switch 2, the drive processing unit 21, the ROM unit 22, D- The A conversion section 23 is the drive output section 3, and the display section
Claims (1)
せられ、このパルス信号入力毎被演算値に定数値を加算
すると共に、所定周期を以て所定値を減算し、演算結果
に基づいて指示計器の指度を決定する指示計器の駆動方
法に於て、減算周期を変更可能にすると共に、減算周期
の変更に対応して加算値を前記減算周期に反比例して変
更してなることを特徴とする指示計器の駆動方法。(1) A pulse signal is emitted every time the object to be measured changes by a predetermined amount, and a constant value is added to the operand value every time this pulse signal is input, and a predetermined value is subtracted at a predetermined period, and instructions are given based on the calculation result. A driving method for an indicating instrument that determines the index of the instrument is characterized in that the subtraction cycle is changeable, and in response to the change in the subtraction cycle, the addition value is changed in inverse proportion to the subtraction cycle. A method of driving an indicating instrument.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25268689A JPH03113379A (en) | 1989-09-28 | 1989-09-28 | Driving method for indicating instrument |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25268689A JPH03113379A (en) | 1989-09-28 | 1989-09-28 | Driving method for indicating instrument |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03113379A true JPH03113379A (en) | 1991-05-14 |
Family
ID=17240831
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25268689A Pending JPH03113379A (en) | 1989-09-28 | 1989-09-28 | Driving method for indicating instrument |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03113379A (en) |
-
1989
- 1989-09-28 JP JP25268689A patent/JPH03113379A/en active Pending
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