JPH0311143B2 - - Google Patents

Info

Publication number
JPH0311143B2
JPH0311143B2 JP57002574A JP257482A JPH0311143B2 JP H0311143 B2 JPH0311143 B2 JP H0311143B2 JP 57002574 A JP57002574 A JP 57002574A JP 257482 A JP257482 A JP 257482A JP H0311143 B2 JPH0311143 B2 JP H0311143B2
Authority
JP
Japan
Prior art keywords
transmission
register
out shift
character
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57002574A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58120347A (ja
Inventor
Masaki Tsucha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP57002574A priority Critical patent/JPS58120347A/ja
Publication of JPS58120347A publication Critical patent/JPS58120347A/ja
Publication of JPH0311143B2 publication Critical patent/JPH0311143B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)
JP57002574A 1982-01-11 1982-01-11 回線アダプタ Granted JPS58120347A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57002574A JPS58120347A (ja) 1982-01-11 1982-01-11 回線アダプタ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57002574A JPS58120347A (ja) 1982-01-11 1982-01-11 回線アダプタ

Publications (2)

Publication Number Publication Date
JPS58120347A JPS58120347A (ja) 1983-07-18
JPH0311143B2 true JPH0311143B2 (enrdf_load_stackoverflow) 1991-02-15

Family

ID=11533139

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57002574A Granted JPS58120347A (ja) 1982-01-11 1982-01-11 回線アダプタ

Country Status (1)

Country Link
JP (1) JPS58120347A (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06105923B2 (ja) * 1986-08-08 1994-12-21 日本電気株式会社 通信制御装置
JPH06105922B2 (ja) * 1986-08-08 1994-12-21 日本電気株式会社 通信制御装置

Also Published As

Publication number Publication date
JPS58120347A (ja) 1983-07-18

Similar Documents

Publication Publication Date Title
US6925512B2 (en) Communication between two embedded processors
US6038607A (en) Method and apparatus in a computer system having plural computers which cause the initiation of functions in each other using information contained in packets transferred between the computers
US4494190A (en) FIFO buffer to cache memory
US5623606A (en) Communication control method and apparatus for performing high speed transfer of data by controlling transfer starting times
US4637015A (en) Packet transmission and reception via a shared DMA channel
US3904829A (en) Demand driven multiplexing system
US20060047754A1 (en) Mailbox interface between processors
US6363076B1 (en) Phantom buffer for interfacing between buses of differing speeds
US5583894A (en) Slip buffer for synchronizing data transfer between two devices
US5228129A (en) Synchronous communication interface for reducing the effect of data processor latency
US5619653A (en) Buffer device with resender
JPH0311143B2 (enrdf_load_stackoverflow)
JPS6359042A (ja) 通信インタ−フエイス装置
JPS5819062A (ja) 回線アダプタ
JP3192009B2 (ja) 転送制御方式
EP0285335B1 (en) Data communication system and method
JP2760280B2 (ja) 通信データ交換装置および該交換装置を用いた通信システム
JPH07281950A (ja) データ記憶装置をアクセスする方法及びメモリアクセス制御装置
JPH023345B2 (enrdf_load_stackoverflow)
JP2625396B2 (ja) 受信データ処理装置
JPH03150943A (ja) 通信装置
US5644292A (en) Alarm termination apparatus
JPH02141862A (ja) データ転送制御方式
JPH023343B2 (enrdf_load_stackoverflow)
KR100208280B1 (ko) 선입선출 제어부를 갖는 데이터 전송 장치