JPH03104223A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPH03104223A JPH03104223A JP24302389A JP24302389A JPH03104223A JP H03104223 A JPH03104223 A JP H03104223A JP 24302389 A JP24302389 A JP 24302389A JP 24302389 A JP24302389 A JP 24302389A JP H03104223 A JPH03104223 A JP H03104223A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon wafer
- wafer
- silicon
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000004065 semiconductor Substances 0.000 title claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 91
- 239000010703 silicon Substances 0.000 claims abstract description 91
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 91
- 235000012431 wafers Nutrition 0.000 abstract description 80
- 239000010408 film Substances 0.000 abstract description 66
- 239000010409 thin film Substances 0.000 abstract description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052760 oxygen Inorganic materials 0.000 abstract description 2
- 239000001301 oxygen Substances 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 239000000758 substrate Substances 0.000 description 16
- 238000000034 method Methods 0.000 description 12
- 238000005498 polishing Methods 0.000 description 12
- 238000005530 etching Methods 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000008119 colloidal silica Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
Ｓｏｌ（シリコンオンインシェレータ）基板の製造方法
の改良に関し、
素子の形成されるシリコン層を、ウェーハの全域にわた
って均一な厚さに薄膜化することを可能にする張り合わ
せＳｏｌ基板の製造方法を提供することを目的とし、
第１のシリコンウェーハ上に第１の酸化膜を形成し、こ
の第１の酸化膜を一部領域から除去し、次いで、この第
１の酸化膜の除去された領域の前記の第１のシリコンウ
エー八をエッチングして凹部を形成し、次に、第２のシ
リコンウェーハ上に第２の酸化膜を、その厚さが前記の
第１の酸化膜の厚さより厚く、前記の凹部の深さより薄
くなるように形成し、この第２の酸化膜を一部領域から
除去し、前記の第１のシリコンウエーハの前記の凹部に
対応する領域に第２の酸化膜よりなる凸部を形成し、前
記の第１のシリコンウエー八と前記の第２のシリコンウ
ェーハとを、前記の凹部と前記の凸部とが嵌合するよう
に重ね合わせて接着し、前記の第１のシリコンウエー八
を、前記の第２の酸化膜よりなる凸部をストッパとして
選択研磨をなしてその厚さを減少するように構成する．
（産業上の利用分野）
本発明は、Ｓｏｌ（シリコンオンインシエレータ）基板
の製造方法の改良に関する．
〔従来の技術〕
表面に酸化膜の形成された２枚のシリコンウェーハを重
ね合わせ、熱処理をなして相互に接着した後、一方のシ
リコンウエー八を薄膜化した、いわゆる張り合わせＳｏ
１基板は、これをＬＳＩ用基板として使用した時に、集
積度の向上、素子特性の高速化、耐放射線特性の向上等
の面で勝れた或果が得られる．本発明はこの張り合わせ
ＳＯＩ基板の製造方法の改良に関するものである．従来
の張り合わせＳｏ１基板の製造過程において使用される
シリコンウエー八の薄膜化の方法としては、選択エッチ
ング法と高精度平面研削法とが知られている．
選択エッチング法とは、第２図に示すように、ｐゝ型シ
リコンウェーハまたはｎ９型シリコンウェーハ３上に、
ＣＶＤ法を使用してそれぞれ同一導電型のｐ型またはｎ
型のシリコン層３１を形或した後、酸化して表面に酸化
膜３２を形成し、第３図に示すように、ｐ型またはｎ型
のシリコンＪｉ３１が形成されている方の面を、酸化膜
４１の形成されている別のシリコンウェーハ４上に重ね
、熱処理をなして相互に接着し、次いで、シリコンの抵
抗率に応じてエッチング速度が異なるエッチング液、例
えばフッ酸と硝酸と酢酸とをｔ：３：Ｓの割合で含有す
る混酸液を使用してｐ゛型またはｎ゛型シリコンウェー
ハ３を選択的にエッチング除去して、均一な厚さのｐ型
またはｎ型シリコン層３１を酸化膜３２・４１上に残留
し、Ｓｏｌ基板を形成するものである．
なお、高精度平面研削法とは、表面に酸化膜の形成され
た２枚のシリコンウェーハを重ね合わせ、熱処理をなし
て相互に接着した後、一方のシリコンウェーハを精度の
高い平面研削装置を使用して薄膜化してｓｏ ｒｇ板を
形成する平面研削法である．
〔発明が解決しようとする課題〕
Ｓｏｌ基板を使用してＬＳＩを製造する場合に、素子の
形成されるシリコン層の厚さが薄いほど、高集積化、高
速化が可能であり、また、耐放射線特性も向上する。[Detailed Description of the Invention] [Summary] Regarding the improvement of the manufacturing method of Sol (Silicon on Insulator) substrates, it is possible to thin the silicon layer on which elements are formed to a uniform thickness over the entire wafer. The purpose of the present invention is to provide a method for manufacturing a bonded Sol substrate, in which a first oxide film is formed on a first silicon wafer, this first oxide film is removed from a partial region, and then this first oxide film is removed from a partial region. The first silicon wafer 8 is etched in the area where the first oxide film has been removed to form a recess, and then a second oxide film is formed on the second silicon wafer so that the thickness thereof is as described above. The second oxide film is formed to be thicker than the thickness of the first oxide film and thinner than the depth of the recess, and the second oxide film is removed from a partial region to correspond to the recess of the first silicon wafer. A convex portion made of a second oxide film is formed in the area where the convex portion is formed, and the first silicon wafer and the second silicon wafer are connected such that the concave portion and the convex portion fit together. They are stacked and bonded together, and the first silicon wafer is selectively polished using the convex portion of the second oxide film as a stopper to reduce its thickness.
(Industrial Application Field) The present invention relates to an improvement in a method for manufacturing a Sol (silicon on insulator) substrate. [Prior art] Two silicon wafers with oxide films formed on their surfaces are stacked and bonded to each other through heat treatment, and then one of the silicon wafers is made into a thin film, so-called bonded SO.
When this substrate is used as an LSI substrate, superior results can be obtained in terms of improved integration, faster device characteristics, and improved radiation resistance characteristics. The present invention relates to an improvement in the manufacturing method of this bonded SOI substrate. Selective etching and high-precision surface grinding are known methods for thinning silicon wafers used in the conventional manufacturing process of bonded So1 substrates. The selective etching method is, as shown in FIG.
p-type or n-type of the same conductivity type using CVD method.
After forming the mold silicon layer 31, it is oxidized to form an oxide film 32 on the surface, and as shown in FIG. The silicon wafer 4 is placed on top of another silicon wafer 4 on which a film 41 has been formed, and is bonded to each other through heat treatment, and then an etching solution having different etching rates depending on the resistivity of the silicon, such as hydrofluoric acid, nitric acid, and acetic acid, is applied. The p-type or n-type silicon wafer 3 is selectively etched away using a mixed acid solution containing a ratio of t:3:S to oxidize the p-type or n-type silicon layer 31 with a uniform thickness. It remains on the films 32 and 41 and forms a Sol substrate. The high-precision surface grinding method involves stacking two silicon wafers with oxide films on their surfaces, bonding them together through heat treatment, and then grinding one of the silicon wafers using a high-precision surface grinding device. This is a surface grinding method in which the SRG plate is formed by forming a thin film. [Problem to be solved by the invention] When manufacturing LSI using a Sol substrate, the thinner the silicon layer on which the element is formed, the higher the integration and speed, and the higher the durability. Radiation properties are also improved.
ところが、選択エッチング法を使用して素子の形成され
るシリコン層を薄膜化する場合には、選択エッチング完
了後に、エッチングされたｐ型またはｎ型シリコン層３
１の表面の平坦化とオートドーブ領域の除去とを目的と
する仕上げ研磨を必要とするので、この仕上げ研磨によ
ってシリコン層の厚さにばらつきが生ずる．また、高精
度平面研削法を使用して素子の形成されるシリコン層を
薄膜化する場合には、素子の形成されない支持側シリコ
ンウヱーハ表面の凹凸が、そのま＼薄膜化後のシリコン
層の厚さのばらつきとなって現れる．このため、一般に
±０．５ｎ以上の厚さのばらつきが発生するので、シリ
コン層の厚さを０．５ｎ以下に薄く形成しようとすると
、部分的に下地の酸化膜が露出してしまい、良質のＳｏ
ｌ基板を製造することは不可能である．
本発明の目的は、この欠点を解消することにあり、素子
の形成されるシリコン層を、ウェーハの全域にわたって
均一な厚さに薄膜化することを可能にする張り合わせＳ
ｏ１基板の製造方法を提供することにある．
〔課題を解決するための手段〕
上記の目的は、第Ｉのシリコンウエーハ（１）上に第１
の酸化Ｉｌｌ（１１）を形成し、この第ｌの酸化膜（１
１）を一部領域から除去し、次いで、この第１の酸化膜
（１１）の除去された領域の前記の第１のシリコンウェ
ーハ（１）をエッチングして凹部（１２）を形成し、次
に、第２のシリコンウェーハ（２）上に第２の酸化膜（
２１）を、その厚さが前記の第１の酸化膜（１１）の厚
さより厚く、前記の凹部（１２）の深さより薄くなるよ
うに形成し、この第２の酸化膜（２１）を一部領域から
除去し、前記の第１のシリコンウェーハ（１）の前記の
凹部（１２）に対応する領域に第２の酸化膜（２１）よ
りなる凸部（２２）を形成し、前記の第１のシリコンウ
ェーハ（１）と前記の第２のシリコンウェーハ（２）と
を、前記の凹部（１２）と前記の凸部（２２）とが嵌合
するように重ね合わせて接着し、前記の第１のシリコン
ウェーハ（１）を、前記の第２の酸化Ｍ （２１）より
なる凸部（２２）をストツパとして選択研磨をなしてそ
の厚さを減少する半導体装置の製造方法によって達威さ
れる．〔作用〕
本発明に係るＳｏｌ基板の製造方法においては、支持側
ウエー八となる第２のシリコンウェーハ２に形成された
第２の酸化膜２１の厚さが、素子側ウェーハとなる第ｌ
のシリコンウエーハ１に形成された第１の酸化膜１１の
厚さより厚く形成されているので、第１のシリコンウェ
ーハ１と第２のシリコンウェーハ２とを、第１のシリコ
ンウェーハｌに形成された凹部１２と第２のシリコンウ
ェーハ２に形成された第２の酸化膜２１よりなる凸部２
２とが嵌合するように重ね合わせて、第１の酸化膜１１
と第２のシリコンウェーハ２とを接着し、次いで、シリ
コンに対する研磨速度より酸化膜に対する研磨速度の方
が小さい選択研磨法を使用し、第２の酸化膜２１よりな
る凸部２２をストツパとして第１のシリコンウェーハＩ
を選択研磨すれば、第１のシリコンウェーハ１は第１の
酸化膜１１の厚さと第２の酸化１１１２１の厚さとの差
に相当する厚さに、ウ工一ハ全域において均一に薄膜化
される．〔実施例〕
以下、図面を参照して、本発明の一実施例に係るＳｏｌ
基板の製造方法について説明する．第１図（ａ）参照
Ｓｏｌ基板の素子側ウエー八となる第１のシリコンウエ
ーハ１を約１，１００″Ｃの温度において約１時間スチ
ーム酸化して、厚さ約１ｉｒｍの第１の酸化膜ｌ１を形
成し、支持側ウエーハとなる第２のシリコンウェーハ２
を約１．１００゜Ｃの温度において約２時間スチーム酸
化して、厚さ約１．５ｎの第２の酸化膜２１を形戒する
．
第ｌ図（ｂ）参照
第１のシリコンウェーハ１に形成されている第ｌの酸化
膜１１をバターニングして一部領域から除去し、さらに
、第１の酸化膜ｌ１の除去された領域の第１のシリコン
ウェーハ１をエッチングして、全体の深さが５ｎ程度の
凹部１２を形成する．第ｌ図（ｃ）参照
第２のシリコンウェーハ２に形成されている第２の酸化
膜２１をバターニングして、第ｌのシリコンウェーハｌ
に形成された凹部１２に対応する領域を除く領域から除
去して、第２の酸化膜よりなる凸部２２を形成する．
第１図（ｄ）参照
第１のシリコンウェーハ１の凹部１２と第２のシリコン
ウェーハ２の凸部２２とが嵌合するように第１のシリコ
ンウェーハ１と第２のシリコンウェーハ２とを重ね合わ
せ、酸素雰囲気中において約１，１００゜Ｃの温度に約
３時間加熱して、第１のシリコンウェーハ１に形成され
た第１の酸化膜１１と第２のシリコンウェーハ２とを相
互に接着する．または、ウェーハ１とウェーハ２との間
にパルス電圧を印加し、静電圧力を使用して接着しても
よい．この場合には、温度を９００″Ｃとし、パルス電
圧を±３００Ｖとするとよい．
第１図（ｅ）参照
第１のシリコンウェーハｌを、その厚さが数ｎ以下にな
るまで研削し、次いで、エチレンジアミンとコロイダル
シリカとを研磨液とする選択研磨をなして、第１のシリ
コンウェーハ１をさらに薄膜化する。この研磨液に対す
るシリコンと酸化膜との研磨速度は５００ ： ｌであ
るので、酸化膜が露出したところで研磨速度が大幅に低
下する．この特性を利用して、第２のシリコンウェーハ
２上に形成された第２の酸化膜よりなる凸部２２がウェ
ーハ全域において露出したところで研磨を停止して素子
側シリコン層１３を形戒する．素子側シリコン層１３の
厚さは、第２のシリコンウェーハ２に形或された第２の
酸化ｊ！２１よりなる凸部２２の厚さ１．５ｎと第１の
シリコンウェーハ１に形成された第１の酸化膜１１の厚
さ１ｎとの差に相当する０．５ｎとなり、しかも、ウエ
ーハ全域にわたって均一に形成される．
〔発明の効果〕
以上説明せるとおり、本発明に係る半導体装置の製造方
法においては、支持側ウエー八となる第２のシリコンウ
エー八に形戒する第２の酸化膜を、素子側ウェーハとな
る第１のシリコンウェーハに形成する第１の酸化膜の厚
さより厚く形成し、この第２の酸化膜よりなる凸部と第
１のシリコンウエー八に形成された凹部とを嵌合させて
、第２のシリコンウエー八と第ｌのシリコンウェーハに
形戒された第ｌの酸化膜とを相互に接着させた後、第１
のシリコンウエー八を選択研磨すれば、第２の酸化膜よ
りなる凸部がストッパとして機能するので、素子側−ウ
ェー八となる第１のシリコンウ工一ハは、第１の酸化膜
の厚さと第２の酸化膜の厚さとの差に相当する厚さに、
ウェーハの全域にわたって均一に薄膜化され、良質のＳ
ｏ１基板が再現性よく形成される．However, when selective etching is used to thin the silicon layer on which elements are formed, the etched p-type or n-type silicon layer 3 is removed after selective etching is completed.
Since final polishing is required for the purpose of flattening the surface of 1 and removing the autodove region, this final polishing causes variations in the thickness of the silicon layer. In addition, when thinning the silicon layer on which elements are formed using a high-precision surface grinding method, the unevenness of the surface of the supporting silicon wafer on which elements are not formed will remain the same as the thickness of the silicon layer after thinning. This appears as a variation in . For this reason, there is generally a variation in thickness of ±0.5n or more, so if you try to make the silicon layer thinner than 0.5n, the underlying oxide film will be partially exposed, resulting in a high-quality silicon layer. So
It is impossible to manufacture l substrates. The purpose of the present invention is to eliminate this drawback, and to make it possible to thin the silicon layer on which elements are formed to a uniform thickness over the entire area of the wafer.
The purpose of this invention is to provide a method for manufacturing an o1 substrate. [Means for Solving the Problems] The above purpose is to place a first silicon wafer (1) on a first
An oxide film (11) is formed, and this lth oxide film (11) is formed.
1) is removed from a partial area, and then the first silicon wafer (1) is etched in the area where the first oxide film (11) has been removed to form a recess (12), and then Then, a second oxide film (
21) is formed so that its thickness is thicker than the thickness of the first oxide film (11) and thinner than the depth of the recess (12), and this second oxide film (21) is A convex portion (22) made of the second oxide film (21) is formed in a region of the first silicon wafer (1) corresponding to the concave portion (12). The first silicon wafer (1) and the second silicon wafer (2) are overlapped and bonded so that the recess (12) and the projection (22) fit together, and The first silicon wafer (1) is selectively polished using the convex portion (22) made of the second oxidized M (21) as a stopper to reduce its thickness. Ru. [Operation] In the method for manufacturing a Sol substrate according to the present invention, the thickness of the second oxide film 21 formed on the second silicon wafer 2, which will become the supporting side wafer, is equal to the thickness of the second oxide film 21, which will become the element side wafer.
The first oxide film 11 is formed thicker than the first oxide film 11 formed on the first silicon wafer 1, so the first silicon wafer 1 and the second silicon wafer 2 are Convex portion 2 consisting of concave portion 12 and second oxide film 21 formed on second silicon wafer 2
The first oxide film 11
and the second silicon wafer 2, and then using a selective polishing method in which the polishing rate for the oxide film is lower than the polishing rate for the silicon, the convex portion 22 made of the second oxide film 21 is used as a stopper. 1 silicon wafer I
By selectively polishing, the first silicon wafer 1 is uniformly thinned over the entire wafer to a thickness corresponding to the difference between the thickness of the first oxide film 11 and the thickness of the second oxide film 11121. Ru. [Example] Hereinafter, with reference to the drawings, Sol according to an example of the present invention will be described.
We will explain the manufacturing method of the board. Referring to FIG. 1(a), the first silicon wafer 1, which will become the element side wafer 8 of the Sol substrate, is steam oxidized at a temperature of about 1,100″C for about 1 hour to form a first oxide film with a thickness of about 1irm. A second silicon wafer 2 that forms l1 and becomes a supporting wafer
is steam oxidized at a temperature of about 1.100° C. for about 2 hours to form a second oxide film 21 with a thickness of about 1.5 nm. Refer to FIG. 1(b), the first oxide film 11 formed on the first silicon wafer 1 is removed from a partial region by buttering, and further, the first oxide film 11 formed on the first silicon wafer 1 is removed from the removed region. The first silicon wafer 1 is etched to form a recess 12 with a total depth of about 5n. Refer to FIG. 1(c), the second oxide film 21 formed on the second silicon wafer 2 is buttered, and the
The convex portion 22 made of the second oxide film is formed by removing the second oxide film from the region excluding the region corresponding to the concave portion 12 formed in the second oxide film. Refer to FIG. 1(d). The first silicon wafer 1 and the second silicon wafer 2 are stacked so that the recess 12 of the first silicon wafer 1 and the projection 22 of the second silicon wafer 2 fit together. The first oxide film 11 formed on the first silicon wafer 1 and the second silicon wafer 2 are bonded together by heating at a temperature of about 1,100°C for about 3 hours in an oxygen atmosphere. do. Alternatively, a pulse voltage may be applied between wafer 1 and wafer 2 to bond them using electrostatic force. In this case, it is preferable to set the temperature to 900"C and the pulse voltage to ±300V. Refer to FIG. 1(e). Grind the first silicon wafer l until its thickness becomes several nm or less, The first silicon wafer 1 is further thinned by selective polishing using ethylenediamine and colloidal silica as a polishing liquid.Since the polishing rate of silicon and oxide film with respect to this polishing liquid is 500:l, the oxidation The polishing rate decreases significantly when the film is exposed.Using this characteristic, polishing is performed when the convex portions 22 made of the second oxide film formed on the second silicon wafer 2 are exposed over the entire wafer. The thickness of the element-side silicon layer 13 is equal to the thickness 1 of the convex portion 22 made of the second oxidized layer 21 formed on the second silicon wafer 2. The thickness is 0.5n, which corresponds to the difference between .5n and the thickness 1n of the first oxide film 11 formed on the first silicon wafer 1, and is formed uniformly over the entire wafer. [Effects of the Invention] As explained above, in the method for manufacturing a semiconductor device according to the present invention, the second oxide film formed on the second silicon wafer 8, which becomes the support side wafer, is transferred to the first silicon wafer 8, which becomes the element side wafer. The second oxide film is formed to be thicker than the first oxide film, and the second oxide film is formed to be thicker than the first oxide film, and the second silicon wafer 8 is formed by fitting the convex portion made of the second oxide film into the recess formed in the first silicon wafer 8. and the l-th oxide film formed on the l-th silicon wafer are bonded to each other.
If the silicon wafer 8 is selectively polished, the convex portion made of the second oxide film functions as a stopper, so that the first silicon wafer 8, which is the element side wafer, is polished with the thickness of the first oxide film. The thickness corresponds to the difference between the thickness of the second oxide film,
The film is uniformly thinned over the entire area of the wafer and has high quality S.
o1 substrate is formed with good reproducibility.
第１図（ａ）〜第１図（ｅ）は、本発明の一実施例に係
るＳＯＩ基板の製造工程図である．第２図〜第４図は、
従来技術に係る選択エッチング法を使用するＳＯＩ基板
の製造工程図である．第１のシリコンウェーハ、
第１の酸化膜、
凹部、
素子側シリコン層、
第２のシリコンウェーハ、
第２の酸化膜、
凸部、
ｐ０型またはｎ′″型シリコンウェーハ、ｐ型またはｎ
型シリコン層、
酸化膜、
シリコンウェーハ、
酸化膜．FIG. 1(a) to FIG. 1(e) are manufacturing process diagrams of an SOI substrate according to an embodiment of the present invention. Figures 2 to 4 are
1 is a manufacturing process diagram of an SOI substrate using a selective etching method according to the prior art. First silicon wafer, first oxide film, recess, element side silicon layer, second silicon wafer, second oxide film, protrusion, p0 type or n''' type silicon wafer, p type or n
mold silicon layer, oxide film, silicon wafer, oxide film.
Claims (1)
）を形成し、 該第１の酸化膜（１１）を一部領域から除去し、次いで
、該第１の酸化膜（１１）の除去された領域の前記第１
のシリコンウェーハ（１）をエッチングして凹部（１２
）を形成し、 第２のシリコンウェーハ（２）上に第２の酸化膜（２１
）を、その厚さが前記第１の酸化膜（１１）の厚さより
厚く、前記凹部（１２）の深さより薄くなるように形成
し、 該第２の酸化膜（２１）を一部領域から除去し、前記第
１のシリコンウェーハ（１）の前記凹部（１２）に対応
する領域に第２の酸化膜（２１）よりなる凸部（２２）
を形成し、 前記第１のシリコンウェーハ（１）と前記第２のシリコ
ンウェーハ（２）とを、前記凹部（１２）と前記凸部（
２２）とが嵌合するように重ね合わせて接着し、 前記第１のシリコンウェーハ（１）を、前記第２の酸化
膜（２１）よりなる凸部（２２）をストッパとして選択
研磨をなしてその厚さを減少する工程を有することを特
徴とする半導体装置の製造方法。[Claims] A first oxide film (11) is formed on a first silicon wafer (1).
), the first oxide film (11) is removed from a partial region, and then the first oxide film (11) is removed from the region where the first oxide film (11) is removed.
The silicon wafer (1) is etched to form a recess (12).
), and a second oxide film (21) is formed on the second silicon wafer (2).
) is formed so that its thickness is thicker than the thickness of the first oxide film (11) and thinner than the depth of the recess (12), and the second oxide film (21) is formed from a part of the region. Then, a convex portion (22) made of a second oxide film (21) is formed in a region of the first silicon wafer (1) corresponding to the concave portion (12).
forming the first silicon wafer (1) and the second silicon wafer (2) into the concave portion (12) and the convex portion (
22) are overlapped and bonded so that they fit together, and the first silicon wafer (1) is selectively polished using the convex portion (22) made of the second oxide film (21) as a stopper. 1. A method of manufacturing a semiconductor device, comprising the step of reducing its thickness.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24302389A JPH03104223A (en) | 1989-09-19 | 1989-09-19 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24302389A JPH03104223A (en) | 1989-09-19 | 1989-09-19 | Manufacturing method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03104223A true JPH03104223A (en) | 1991-05-01 |
Family
ID=17097722
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24302389A Pending JPH03104223A (en) | 1989-09-19 | 1989-09-19 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03104223A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5399233A (en) * | 1991-12-05 | 1995-03-21 | Fujitsu Limited | Method of and apparatus for manufacturing a semiconductor substrate |
-
1989
- 1989-09-19 JP JP24302389A patent/JPH03104223A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5399233A (en) * | 1991-12-05 | 1995-03-21 | Fujitsu Limited | Method of and apparatus for manufacturing a semiconductor substrate |
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