JPH03104057A - Floppy disk control circuit - Google Patents

Abstract

PURPOSE:To automatically and instantaneously switch a system clock when the same drive is accessed after the second access by storing the signal of a counter circuit in a RAM when the synchronization of a phase synchronizing circuit can be obtained. CONSTITUTION:By using an index signal (b) from a floppy disk drive FDD, count signals (h) and (i) from a two-bit counter circuit 5 are changed and stored in a RAM 6. The signals are inputted through a selecting circuit 8 to a decode circuit 9 and a clock select signal (l) is outputted. According to a signal (e), a clock select circuit 10 switches the system clock of a floppy disk control circuit FDC. When lock is already completed, stored contents h1 and i1 of the RAM 6 are inputted through the circuit 8 to the circuit 9 and the system clock of the FDC can be automatically and instantaneously switched.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a floppy disk control circuit that controls switching of the system clock of a floppy disk controller (hereinafter referred to as FDC) using a phase synchronized circuit output and a read operation signal. ．． (Prior Art) In recent years, floppy disk drives (hereinafter referred to as FDDs) have come in a variety of types, including 5.25-inch, 3.5-inch, double-density storage, and high-density storage. Along with this, if you connect an external FDD with a different size or recording density in addition to the FDD built into the personal computer, the data transfer will be different from the FDD inside the personal computer.
The FDC will no longer be able to read or write data. Therefore, in such cases, data read/write operations were performed by automatically selecting and switching the FDC system clock that matched the data transfer rate each time an index signal from the FDD was input. (Problem to be Solved by the Invention) However, in the conventional method described above, when reading and writing operations are performed on multiple FDDs, the system clock of the FDC that is compatible with the data transfer speed of each FDD is changed from one FDD to another. There was a problem in that each user had to go through a process of selecting and switching in order from the beginning.

The present invention solves the above-mentioned conventional problems, and the next time access is made to a drive that has selected an FDC system clock that is compatible with the data transfer rate of the FDD. The object of the present invention is to provide a floppy disk control circuit that can instantly switch the system without having to switch the FDC system clock sequentially from the beginning.

(Means for Solving the Problems) In order to achieve the above object, the present invention includes a floppy disk control circuit that stores FDC system clock information suitable for the data transfer speeds of a plurality of FDDs in a random access memory (RAM). This allows the system clock to be switched instantaneously.

(Function) Therefore, with the above configuration, it is possible to read and write data from a plurality of FDDs having different data transfer speeds using the same FDC.

(Embodiment) FIG. 1 shows a block structure of a proppy disk control circuit in an embodiment of the present invention, and FIGS. 2 and 3 show an example of main input/output signals in FIG. This shows a time chart. In FIG. 1, reference numeral 1 denotes a phase-locked circuit, which inputs a phase-locked circuit system clock O and read data a, and generates a sampling clock b synchronized therewith. Reference numeral 2 denotes a phase synchronization detection circuit which inputs read data a and sampling clock b, detects that both signals are synchronized, and outputs a lock signal C. 3 is a flip-flop circuit (F/F), and the F/F is activated by lock signal C? and reset the F/F with the reset signal R2. 4 is an AND gate which inputs the output of flip-flop 3, the read operation signal e, and the index signal f that is output every time the floppy disk rotates. 5 is counted by the output of AND gate 4, reset by reset signal R2, and count signal h
, i, 6 is a RAM, and when the read/write control signal d1 is low (L), the count signals h, i and the output d of the flip-flop circuit 3, and d■ is high (H
), the memory content hllll is output. 7 is a reset circuit that outputs a reset signal R2 every time the reset signal R1 changes to 11H I+ or the drive select signal Jtk, and 8 is the RAM output dU
When d1 is "H", count signals h and i are set, and when d1 is "H", R is set.
Select AM output hllll and h2tx. A selection circuit 9 decodes the output of the selection circuit 8 and outputs a clock selection signal α. A clock select circuit 10 selects a system clock m or n for a floppy disk control circuit from a clock source according to a clock select signal and outputs a system clock O for a phase synchronized circuit. 1l is a frequency dividing circuit which inputs the phase synchronized circuit system clock O and generates the FDC system clock p by dividing the frequency by 1/n.

The phase synchronization detection circuit 2 is a known circuit that considers that the sampling clock b and the read data a are locked when the relationship of l:2 is sampled approximately 20 times in the sync byte of the floppy disk, and the lock signal C is is “H” when locked, “L” when unlocked
Output. In addition, the reset signal R4 is “H” in the RAM6.
'', all are reset to "L", and the output d■ always outputs the stored content d1.

Next, the operation of the above embodiment will be explained. In the above embodiment, the reset signal R1 sets the output d of the F/F3 to "L" and resets the 2-pit counter circuit 5 and the RAM 6 due to II H I+. Next, when the read operation signal e becomes "riH", while the lock signal C is "L", A is synchronized with the rising edge of the index signal f.
The output g of the ND gate 4 becomes "H", the counter circuit 5 starts counting, and the count signals h and i output from the counter circuit begin to change. At this time, the drive select signal Jyk from the FDC selects the register corresponding to the drive in the RAM 6, but while the read/write control signal d1 is It L 71, the count signals h, i of the counter circuit 5 and the output d of the F/F3 are The selection circuit 8 outputs count signals h, i while the read/write control signal d1 is "LH".The decode circuit 9 uses these count signals h, i to output a clock select signal α, The select circuit 10 selects the system clock m or n of the floppy disk control circuit using the clock select signal α, and changes the system clock O of the phase synchronized circuit. After that, when the phase synchronization detection circuit 2 detects that the phase synchronization circuit 1 is synchronized, the lock signal C becomes t.
iH" and the output d of F/F3 also becomes "H", so even if the index signal f is input, the output g of the AND gate 4 becomes a constant value. In addition, in the RAM 6, the output d of F/F3 becomes "H".
When becomes “H”, it is remembered that the F/F output d has become “H”, and the read/write control signal d also becomes “H”.
Output It. Therefore, the RAM 6 outputs the memory content h■l 11 when the phase synchronization circuit 1 is synchronized,
Since the selection circuit 8 outputs the memory contents of the RAM, the system clock ○ of the phase synchronized circuit and the system clock p of the FDC select and hold the system clock when they are synchronized.

In this way, the system clock of the FDC is selected for the first drive selected after reset by the above-described operation.

Next, if the phase synchronization circuit 1 is synchronized with the selected drive, the read/write control signal d■ is "H", so is it the same? When the count is removed, the stored count signals h and i are output, and the selection circuit 8 stores them in the RAM.
Since the memory contents h,,i■ are outputted, the system clock O of the phase-locked circuit and the system clock p of the FDC are instantly selected and held. Figure 2 shows that for the first drive selected after reset, the floppy disk control circuit system clock m is selected during the period when the clock select signal a is "L", and the system clock n is selected during the period when the clock select signal a is "H". This is an example of a locked state, and the frequency dividing circuit is dividing the frequency by 1/2.

FIG. 3 shows an example in which a drive that has already been locked is selected, and shows an example in which the system clock is switched to n while the clock select signal a is "H".

As described above, according to this embodiment, the index signal f from the FDD is used to change the count signals h, i from the 2-bit counter circuit 5, and the count signals h, i are changed to R.
It is stored in AM6 and input to the decoding circuit 9 via the selection circuit 8 and decoded. The memory contents of RAM 6 can be changed by switching multiple FDC system clocks depending on the lock select signal, or if locking has already been completed.
1, i■ can be input to the decoding circuit 9 via the selection circuit 8 to switch the FCC system clock, so even if multiple FDDs with different data transfer speeds are connected, data can be read and written using the same FDC. It becomes possible to do this.

(Effects of the Invention) As is clear from the above embodiments, the present invention stores in RAM the count signal of the counter circuit when the phase synchronization circuit is synchronized, especially when accessing the same drive for the second time or later. This has the effect of realizing a floppy disk control circuit that can automatically and instantaneously switch the FDC system clock.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a floppy disk control circuit according to an embodiment of the present invention, and FIGS. 2 and 3 are time charts showing an example of main input/output signals in FIG. 1. 1...Phase synchronization circuit, 2...Phase synchronization detection circuit, 3...Flip-flop circuit, 4...A
ND gate, 5... counter circuit, 6...
RAM, 7... Reset circuit, 8... Selection circuit, 9... Decode circuit, lO... Clock select circuit, 11... Frequency divider circuit, a... Read data, b... sampling clock, C
... Lock signal, d ... F/F output, e
... Read operation signal, f ... Index signal, g ... AND gate output, h, i ...
count signal, d...read/write control signal, hyu,11...RAM storage content, h2,i.・
... Selection circuit output, Jek ... Drive select signal, Q ... Clock select signal. m, n ・
...System clock for floppy disk control circuit,
O...System clock for phase synchronized circuit, p ・
... System clock for FDC? ■，

Claims (1)

[Claims] A phase synchronization circuit that generates a sampling clock in synchronization with read data, a phase synchronization detection circuit that inputs the sampling clock and read data and detects that synchronization is established, and an output of the phase synchronization detection circuit and a read operation signal. a random access memory (RAM) that stores or outputs the output signal of the counter circuit according to the drive select signal and the output of the phase synchronization detection circuit; a selection circuit that makes a selection; a decoding circuit that receives the output of the selection circuit as an input; a clock selection circuit that controls switching of a system clock for a phase-locked circuit into at least two stages based on the output of the decoding circuit; A floppy disk control circuit comprising: a frequency dividing circuit that divides the frequency of the output of the circuit.