JPH03102747U - - Google Patents

Info

Publication number
JPH03102747U
JPH03102747U JP1990011553U JP1155390U JPH03102747U JP H03102747 U JPH03102747 U JP H03102747U JP 1990011553 U JP1990011553 U JP 1990011553U JP 1155390 U JP1155390 U JP 1155390U JP H03102747 U JPH03102747 U JP H03102747U
Authority
JP
Japan
Prior art keywords
grounding
signal transmission
wiring
layer substrate
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1990011553U
Other languages
English (en)
Japanese (ja)
Other versions
JP2502994Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990011553U priority Critical patent/JP2502994Y2/ja
Publication of JPH03102747U publication Critical patent/JPH03102747U/ja
Application granted granted Critical
Publication of JP2502994Y2 publication Critical patent/JP2502994Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP1990011553U 1990-02-09 1990-02-09 半導体集積回路装置 Expired - Lifetime JP2502994Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990011553U JP2502994Y2 (ja) 1990-02-09 1990-02-09 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990011553U JP2502994Y2 (ja) 1990-02-09 1990-02-09 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPH03102747U true JPH03102747U (pl) 1991-10-25
JP2502994Y2 JP2502994Y2 (ja) 1996-06-26

Family

ID=31515076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990011553U Expired - Lifetime JP2502994Y2 (ja) 1990-02-09 1990-02-09 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JP2502994Y2 (pl)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5693350A (en) * 1979-12-26 1981-07-28 Mitsubishi Electric Corp Armor of semiconductor device
JPS6037753A (ja) * 1983-08-10 1985-02-27 Nec Corp 半導体装置用パツケ−ジ
JPS63188963A (ja) * 1987-01-31 1988-08-04 Sumitomo Electric Ind Ltd 半導体素子搭載用パツケ−ジ
JPH01191433A (ja) * 1988-01-26 1989-08-01 Fujitsu Ltd 集積回路素子

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5693350A (en) * 1979-12-26 1981-07-28 Mitsubishi Electric Corp Armor of semiconductor device
JPS6037753A (ja) * 1983-08-10 1985-02-27 Nec Corp 半導体装置用パツケ−ジ
JPS63188963A (ja) * 1987-01-31 1988-08-04 Sumitomo Electric Ind Ltd 半導体素子搭載用パツケ−ジ
JPH01191433A (ja) * 1988-01-26 1989-08-01 Fujitsu Ltd 集積回路素子

Also Published As

Publication number Publication date
JP2502994Y2 (ja) 1996-06-26

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term