JPH03100843A - Information processor - Google Patents

Abstract

PURPOSE:To increase the processing speed of a store instruction by transferring the data which are validated by the mask information on the continuous store instructions to main storage device when these continuous store instructions are equal to the same store instructions to the same addresses. CONSTITUTION:A coincidence detecting comparator 12 detects whether the address of a preceding store instruction held in a wait stage address register 8 is equal to the address of a subsequent store instruction or not. A coincidence detecting comparator 13 detects whether the request of a preceding store instruc tion held in a wait stage request register 9 is equal to the request of a subse quent store instruction or not. A mask control part 14 transfers the valid one of the store data on a preceding store instruction and that of a subsequent store instruction received from a store data buffer 7 to a main storage device 21 based on the store mask information. As a result, the processing speed of a store instruction is increased when two continuous store instructions are equal to the same store instructions to the same address of the storage 21.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an information processing apparatus, and more particularly to a high-speed processing method for store instructions in a pipeline processing type information processing apparatus.

BACKGROUND ART Conventionally, in pipeline processing type information processing apparatuses, flushing from a store buffer to a main memory device has been performed in word units of the store buffer.

Therefore, if two store commands for the same address in the main memory are registered in the store buffer consecutively, the main memory 1! It was necessary to access the same address twice.

In such conventional pipeline processing type information processing devices, even if two consecutive store instructions in the store buffer are the same store instructions to the same address in the main memory, the main memory is accessed twice. is necessary,
Since the signal access time between the central processing unit and the main memory is slower than the signal access time within the central processing unit, there is a drawback that store instruction processing cannot be accelerated.

OBJECTS OF THE INVENTION The present invention has been made to eliminate the drawbacks of the conventional ones as described above, and is to improve the speed of store instruction processing when two consecutive store instructions are the same store instruction to the same address in the main memory. The objective is to provide an information processing device that can be used to

Composition of the Invention An information processing device according to the present invention is an information processing device that temporarily holds data stored in a main storage device in response to a store instruction in a store buffer, wherein consecutive store instructions temporarily held in the store buffer are the same. a detection means for detecting whether or not the store instruction is the same for the address; and when the detection means detects that the store instruction is the same for the same address, it is determined that the store data is valid based on the mask information of the consecutive store data. and transfer means for transferring the data to the main storage device.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the store buffer flush pointer (RA
) (hereinafter referred to as a sweep pointer) 1 supplies a sweep address to the store address buffer 4, store request buffer 5, store mask buffer 6, and store data buffer 7, respectively.

As a result, the store address is flushed from the address specified by the flush pointer 1 of the store address buffer 4, and the wait stage address register (WA) is flushed.
The store request is sent to the wait stage request register (WQ) 9 and the match detection comparator 12, and the store request is swept out from the address specified by the sweep pointer 1 of the store request buffer 5 and sent to the wait stage request register (WQ) 9 and the match detection comparator 13.

Further, the store mask information is flushed from the address specified by the sweep pointer 1 of the store mask buffer 6 and sent to the wait stage mask register (WM) 10 and the mask control unit 14, and the store mask information is flushed out from the address specified by the sweep pointer 1 of the store data buffer 7. Store data 1.11 is output from the address specified by wait stage data register (VVD) 11 and selector (WDX) 1.
Sent on 9th.

Store address/request registration pointer (WAO) (
(hereinafter referred to as a registration pointer) 2 supplies an address to the store address buffer 4 and the store request buffer 5.

Therefore, in the store address buffer 4 and the store request buffer 5, a store address and a store request are registered at the address specified by the registration button interface 2.

A store mask/data registration pointer (WAl) (hereinafter referred to as a registration pointer) 3 supplies addresses to a store mask buffer 76 and a store data buffer 7.

Therefore, store mask information and store data are registered in the store mask buffer 6 and store data buffer 7 at the address specified by the registration pointer 3.

The wait stage address register 8 temporarily holds the store address flushed from the store address buffer 4, and sends the store address to the match detection comparator 12 and the store stage address register (SA) 16.

The wait stage request register 9 temporarily holds the store request flushed from the store request buffer 5, and passes the store request to the match detection comparator 13 and the store stage request register (SQ).
)17.

The wait stage mask register 10 temporarily holds the store mask information flushed from the store mask buffer 6, and sends the store mask information to the mask control section 14.

The wait stage data register 11 temporarily holds the store data flushed from the store data buffer 7 and sends the store data to the selector 19.

The match detection comparator 12 compares the store address of the preceding store instruction held in the unique stage address register 8 with the store address of the subsequent store instruction from the store address buffer 4, and applies the comparison result to an AND gate.] Output to 5.

That is, the coincidence detection comparator 12 detects whether the address of the preceding store instruction and the address of the subsequent store instruction are the same address.

The match detection comparator 13 compares the store request of the preceding store instruction held in the store request register 9 with the store request of the subsequent store instruction from the store request buffer 5, and sends the comparison result to the AND gate 15. Output to.

That is, the coincidence detection comparator 13 detects whether the preceding store instruction request and the subsequent store instruction request are the same request.

The mask control unit 14 stores the store mask information of the preceding store instruction held in the wait stage mask register 10 and the store mask of the subsequent store instruction from the store mask buffer 6 in response to the merge instruction from the anime game 1/15. Depending on the information, either the store data of the preceding store instruction held in the wait stage data register 11 or the store data of the subsequent store instruction from the store data buffer 7 is registered in the store stage data register (SD) 20. for each byte.

That is, when a merge is instructed by a merge instruction from the AND gate 15, the mask control unit 14 performs a logical OR operation on the store mask information of the preceding store instruction and the store mask information of the subsequent store instruction, and The calculation result is registered in the store stage mask register (SNl) 18. Both controllers control the selector 19 based on the calculation results to select store data to be registered in the store stage data register 20 from among the store data of the preceding store instruction and the store data of the subsequent store instruction.

! FIG. f12 is a diagram showing details of the mask control section 14 in FIG. 1. In the figure, when the merge instruction from the AND gate 15 is "0", that is, when no merging is performed, the store mask control unit 14 controls the store mask information of the preceding store instruction and the store mask information of the subsequent store instruction. l)', regardless of "1", the store data of the preceding store instruction is stored in the store stage data register 2 +
).

Further, when the merge instruction from the AND gate 15 is "1", that is, when the mask control unit 14 performs the merge (row -),
If the store mask information of the preceding store instruction is “0” and the store mask information of the following store instruction is “0”,
It is determined that the store data of the preceding store instruction is to be registered in the store stage data register 20.

If the store mask information of the preceding store instruction is “0” and the store mask information of the following store instruction is “1”, then
It is determined that the store data of the subsequent store instruction is to be registered in the store stage data register 20.

If the store mask information of the preceding store instruction is “1” and the store mask information of the following store instruction is “1]°, it is determined to register the store data of the preceding store instruction in the store stage data register 20. .

If the store mask information of the preceding store instruction is “1” and the store mask information of the following store instruction is “11”, then
It is determined that the store data of the subsequent store instruction is to be registered in the store stage data register 2o.

FIG. 3 is a time chart showing the operation of one embodiment of the present invention, and FIG. 4 is a diagram showing an example of pipeline processing according to one embodiment of the present invention. In FIG. 4, in pipeline processing according to an embodiment of the present invention, there is an instruction fetch IF stage in which an instruction is fetched from the instruction cache according to an address from an address register (AIC), and an instruction fetch IF stage in which an instruction fetched in this stage is stored in an instruction register. Operand address (AC) that generates a logical address in the address adder based on the operand of this instruction after storing it in (!R)
an address substitution (AT) stage in which the logical address generated in this stage is stored in a logical address register (LAR) and then translated into a physical address in an address translation buffer (TLB); The operand cache access (CA) stage stores the translated physical address in the physical address register (PAR) and then accesses the operand cache using this physical address to read the operand, and the operand read in this stage is stored in the execution register (PAR). EX
Arithmetic execution (EX) to perform calculations on the arithmetic unit after storing in R)
It is divided into six stages: a ST stage and a result storage (ST) stage in which the result calculated in this stage is stored in a read data register (RDR) and then stored in a store buffer.

The calculation results stored in the store buffer are stored in the wait stage register (WD) and store stage register (S).
D) and then transferred to the main storage.

The operation of one embodiment of the present invention will be explained using these FIGS. 1 to 4.

At timing tl, processing of the 5TAI instruction, which is a store instruction, is started, and at timing t2, processing of the 5TA2 instruction, which is a store instruction, is started.

This 5TA2 instruction is processed with an IT (timing) delay of the STA1 instruction from the instruction fetch stage to the result storage stage.

Normally, in store command processing, the timing at which addresses and requests are registered in the store buffer is different from the timing at which data and mask information are registered.

At timing t4, the store address and store request of the STA l instruction are registered in the word positions of the store address buffer 4 and store request buffer 5 indicated by registration pointer 2, respectively, and at timing t7, the store mask information and store data of the 5TAI instruction are stored. The registration buttons of the mask buffer 6 and the store data buffer 7 register f? at the word positions indicated by the f counter 3, respectively. be done.

The store address, store request, store mask information, and store data of the ST^2 instruction are also registered in the store address buffer 4, store request buffer 5, store mask buffer, etc., and store data buffer 7, respectively, due to the IT delay in processing the STA l instruction. be done.

At timing t7, registration of the store data of the 5TAI instruction in the store data buffer 7 is completed, so that both the store address and the store data of the STA1 instruction exist in the store buffer. 'From the word position indicated by the store address of the AI instruction and the store buffer flush pointer 1 of the store data to the WD (wait data) stage (wait stage address register 8.
Uni/f tossage request register 9. Waits Dage Mask Register 10. A flush to the wait stage data register 11) is performed.

Also, at timing t9, sweeping is about to be performed from the word position indicated by the store address of the ST^2 instruction and the store buffer sweep button of the store data.

At this timing, the match detection comparator 12 checks whether the flush address from the store address buffer 4 and the output address from the wait stage address register 8 match.

Further, a match detection comparator 13 checks whether the request flushed from the store request buffer 5 matches the request output from the wait stage request register 9.

As a result, when "1" is output from each of the match detection comparators 12 and 13, it is determined that the 5TA1 instruction and the 5TA2 instruction are the same store request for the same address in the main memory 21, and the store data buffer 7
The data swept out from the storage stage data register 11 and the output data from the weight stage data register 11 are registered in the store stage data register 20 according to the mask value indicated by the mask control unit 14 for each byte.

That is, the mask control unit 14 controls the selector 19,
Which of the store data from the wait stage data register 11 (STAI instruction store data) and the store data from the store data buffer 7 (ST^2 instruction store data) is registered in the store stage data register 20. For each byte, it is determined whether it should be done or not.

At this time, the mask control unit 14 uses the logic between the store mask information from the wait stage mask register 10 (store mask information for the STAI instruction) and the store mask information from the store mask buffer 6 (store mask information for the 8th A2 instruction). Since the sum is calculated, the S stage data register 20 contains the store data masked by the logical sum of the store mask information from the wait stage mask register 10 and the store mask information from the store mask buffer 6. 5 Registered as store data of TAR instruction.

In addition, the value obtained by logically ORing the store mask information from the wait stage mask register 10 and the store mask information from the store mask buffer 6 in the mask control unit] 4 is used as the store mask information full of the 5TAB instruction as the store stage mask. Register 181: Registered.

Furthermore, the value of the wait stage address register 8 is registered in the store stage address register 16, and the value of the wait stage request register 9 is registered in the store stage request register 17.

As described above, at timing t9, the result of merging the store data of the 5TA1 instruction and the store data of the 5TA2 instruction is registered in the store stage data register 20, and at timing 110, it is transferred from the SD (store data) stage to the main storage device 21. Cleaning will be carried out.

That is, from the store stage address register 16, store stage request register 717, store stage mask register 18, and store stage data register 20, the store address, store request, store mask information, and store data of the 5TA3 instruction are stored in the main memory 21, respectively. is swept away.

In this way, two
2 store instructions, i.e. 5 TAI instructions and ST^2
When it is detected by the match detection comparator 12.13 and the AND gate 15 that the instructions are the same store request for the same address of the main memory 21, the store mask information of the 5TAI instruction and the store mask of the ST^2 instruction By merging the store data of the STA1 instruction with the store data of the 5TA2 instruction based on the information and then transferring it to the main memory 21, access to the main memory 21 is reduced by one time when cleaning from the store server couch. can be reduced to times.

Therefore, when two consecutive store instructions are the same store instruction to the same address in the main storage device 21, it is possible to speed up the store instruction processing.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, when consecutive store instructions are detected to be the same store instruction to the same address, the successive store instructions are determined to be valid based on the mask information of each name. By transferring the data to the main memory, it is possible to speed up the store instruction processing when two consecutive store instructions are the same Str instruction to the same address in the main memory. There is an effect.

[Brief explanation of drawings]

The IT diagram is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is! A diagram showing details of the store mask control section in Figure 01,
FIG. 3 is a time chart showing the operation of an embodiment of the present invention, and FIG. 4 is a diagram showing an example of pipeline processing according to an embodiment of the present invention. Explanation of symbols of main parts 4...Store address buffer 5...
Store request buffer 6... Store mask buffer 7... Store data buffer 8... Wait stage 12° Address register 9... Wait stage request register 10... ... Wait stage mask register 11 ... Wait stage data register 13 ... Match detection comparator 14 ...
-Mask control unit 15...AND gater 16...Store stage address register 17...Store stage request register 18...Store stage mask register 19.
...Selector 20...Store stage data register 21.
...Main memory

Claims (1)

[Claims] (1) An information processing device that temporarily holds data stored in the main memory by a store instruction in a store buffer, and whether consecutive store instructions temporarily held in the store buffer are the same store instruction for the same address. a detection means for detecting whether the store instruction is the same for the same address, and a detection means for detecting whether the store instruction is the same for the same address; An information processing device comprising: a transfer means for transferring information.