JPH0432415B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus having a conversion buffer having a plurality of pairs of logical addresses and real addresses in a logical addressing system.

Information processing equipment that performs advanced advance control, is equipped with a cache memory, and has a buffer for converting pairs of logical addresses and real addresses in the logical addressing system, has conventionally performed the prefetching of instruction words and the execution of instructions in parallel. A control method is adopted in which the time spent reading the instruction word from the memory system has as little influence as possible on the execution time of the instruction.

That is, in many cases, a request to read the instruction word of a branch destination prediction instruction (hereinafter referred to as a succeeding instruction) is made to the memory system before the execution result of a preceding branch instruction (hereinafter referred to as a preceding instruction) is known.

Therefore, depending on the execution result of the preceding instruction, the processing of subsequent instructions after the preceding instruction may be invalidated.
It often happens that execution is restarted from an instruction following a preceding instruction. In such a case, the real address corresponding to the logical address due to the read request of the subsequent instruction may not exist in the translation buffer, and the address translation mechanism is forced to perform address translation unrelated to execution. The memory system seen by the execution control unit is closed, and the unnecessary processing of creating a real address corresponding to the logical address of the instruction word of the subsequent instruction causes a delay in execution time.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus that does not cause a delay in execution time due to unnecessary address translation operations when a real address corresponding to a requested logical address does not exist in the translation buffer.

In order to achieve the above object, an information processing device according to the present invention includes an address translation buffer that stores a real address corresponding to a logical address, and when a translated address does not exist in this address translation buffer, converts the logical address into the corresponding real address. In an information processing device having an address translation mechanism that performs translation, a flag indicating that the processing result of a branch instruction is not determined is added to a read request for performing advance control, and a flag is added to the read request for performing advance control, and the address translation buffer When the real address of the logical address does not exist, depending on the state of the flag, wait for an address translation start signal or address translation discard signal from the execution control unit that determines the processing result of the branch instruction, and perform the address translation start signal or address translation discard signal. An address conversion command decoding circuit is provided for receiving a signal and controlling the address conversion mechanism, and activates the address conversion mechanism when the read request is valid, and inhibits activation of the address conversion mechanism when the read request is invalid. It is configured.

According to the above configuration, wasted operations of the address translation mechanism can be eliminated, execution time can be shortened, and the object of the present invention can be completely achieved.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention. In many large-scale information processing devices, for logical addresses that have been accessed in the past, the real address obtained by address conversion at that time is stored in the address conversion buffer 21 as a pair with the logical address. When accessing, the real address corresponding to the logical address is extracted from the address translation buffer 21, and the structure is designed to minimize time delay due to address translation. However, it is difficult for this conversion buffer 21 to have a sufficiently large capacity due to the control system and restrictions on the amount of hardware, and due to the nature of the program, the real address corresponding to the requested logical address is limited to the address conversion buffer 21.
In many cases, the information for converting the data transfer request address issued by the advance control unit 3 and the execution control unit 4 is transferred from the cache memory 24 or the main memory 1 to the data bus 1.
21, 211, spend a lot of time to find the real address, read the data in the cache memory 24 or the main memory 1 using the real address, and transfer the data to the source of the read request. Therefore, avoiding unnecessary address translation processing will greatly contribute to improving performance.

The present invention focuses on this point, and since advance control is performed, it is uncertain whether or not it will actually be used for processing. The read request signal and address signal of the instruction following the branch instruction, and a flag indicating that the use of this request is uncertain, that is, a conversion command wait signal, are sent from the advance control unit 3 to each signal line 322, 321,
323 to the buffer memory control circuit 26.

Next, when the buffer memory control circuit 26 sends a necessary logical address part to the address conversion buffer 21 via the signal line 251, a detection signal indicating whether a corresponding real address exists is sent to the signal line 251.
It is reported from the address translation buffer 21 via the address conversion buffer 21. When it is reported that the buffer memory does not exist, the buffer memory control circuit 26 sends a conversion wait signal 323.
The address conversion command decoding circuit 2 sends an address conversion request from the control line 261 with the information that the address conversion command has been added.
At this time, the address conversion command decoding circuit 27 waits for an address conversion start or discard command signal 441 from the execution control 4.

When the start of address conversion is commanded (in case of branch failure), a conversion instruction is sent to the address conversion mechanism 28 via the signal line 271, while the buffer memory control circuit 26 sends the logical address via the address line 262. . In the address conversion mechanism 28, the address converter 25 is activated under the control of the address conversion control circuit 22, and the index of the table information necessary for conversion is transferred to the buffer memory control circuit 26 through the data line 263 in the same way as in normal data reading. It will be held in

Further, when a command to discard address translation is issued (in case of a successful branch), the address translation request from the buffer memory control circuit 26 is ignored and the operation instruction to the address translation mechanism 28 is discarded. In this way, by suppressing the activation of unnecessary address translation mechanisms, it is possible to prevent valid address translation data from being evicted from the address translation buffer, and to enable early use of the memory buffer control unit for subsequent valid read requests. do.

In this embodiment, an example of predictive pre-fetching of the instruction following a branch instruction has been explained, but if a branch destination instruction is similarly predictively pre-fetched, failure of the branch will be detected and activation of the address translation mechanism will be inhibited. It is also possible to provide a device that suppresses activation of the address translation mechanism when an unnecessary condition is detected.

The present invention, including the above configuration, extends to the entire scope of the claims.

As described in detail above, the present invention speeds up the execution time of an information processing device by controlling activation of an address translation mechanism by an address translation command wait instruction when there is no translation address for a logical address in response to a data read request. It has the effect of measuring the

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of an information processing apparatus according to the present invention. 1... Main memory, 2... Buffer memory control section, 3...
Advance control unit, 4... Execution control unit, 21... Address translation control unit, 22... Address translation control circuit, 25...
Address converter, 26... Buffer memory control circuit, 27... Address conversion command decoding circuit, 28... Address conversion mechanism, 24... Cache memory, 12
1...Main memory read data path, 211...Main memory address and main memory write data path, 231...Instruction word and operand word path, 241...Operand word path, 261...Conversion request signal line by address conversion mechanism waiting for address conversion instruction, 271...Address conversion mechanism activation request signal line, 321...Memory read/write request data path, 323...Address conversion instruction wait signal line, 341...Instruction supply path, 431
...Operand word request path, 441...Address translation mechanism activation start, inhibition instruction signal line.

Claims (1)

[Claims] 1. In an information processing device having an address translation buffer that stores a real address corresponding to a logical address, and an address translation mechanism that translates the logical address into the corresponding real address when the translated address does not exist in this address translation buffer, A flag indicating that the processing result of a branch instruction is not determined is added to a read request for advance control, and the flag is added when the real address of the logical address of the request does not exist in the address translation buffer. Depending on the state, it waits for an address translation start signal or an address translation discard signal from the execution control unit that determines the processing result of the branch instruction.
An address translation command decoding circuit is provided to control the address translation mechanism in response to the address translation start signal or the address translation discard signal, and activates the address translation mechanism when the read request is valid and reads the address when the read request is invalid. An information processing device characterized by being configured to suppress activation of a conversion mechanism.