JPH0294719A - Faulty point detection system for time division multiplex communication system - Google Patents

Abstract

PURPOSE:To detect at which location a fault takes place by providing an inverse logic arithmetic circuit for the processing of a test signal. CONSTITUTION:A reception signal processing unit 30 of a time division multiplexer 3 at the receiver side applies signal processing to a received data 106, a test signal demultiplexing circuit 31 demultiplexes a test signal 107 and inverse logic arithmetic circuits 33a-33n apply the inverse logic arithmetic operation to the test signal 107 using patterns 103a-103n from pattern generating circuits 32a-32n. If a repeater 2A is faulty and the signal therefrom shows all consecutive 0s, the result of the operation with a pattern 103b of a repeater 2B indicates all 0s. Thus, the time division multiplexer 3 at the receiver side can detect a faulty location depending whether any result of the inverse logic arithmetic circuits 33a-33n depicts all 0s or all 1s.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fault detection method for a time division multiplex communication system.

[Conventional technology]

Conventionally, in this type of time division multiplex communication system including multiple relay devices, each relay device has a fault detection circuit.
When a failure occurs in a relay device, the next-stage relay device that detects the failure time-division multiplexes the failure information into a specific time slot of the transmitted data, and then time-division multiplexes it to the next-stage relay device or the receiving side. was transmitting to the device.

[Problem to be solved by the invention]

The failure detection method of the conventional time division multiplex communication system described above detects only the presence or absence of a failure in the relay section based on the failure information time division multiplexed with the received data in the time division multiplexer on the receiving side. Since it is not possible to determine in which relay device in a section a failure has been detected, there is a drawback that it is not easy to detect the failure location, especially when the number of relay stages increases.

[Means to solve the problem]

The failure point detection method for a time division multiplex communication system of the present invention is a time division multiplex communication system that includes a plurality of relay devices that relay signals between two time division multiplex devices in multiple stages. The device includes a transmission signal processing circuit that performs signal processing of transmission data, a test signal generation circuit that generates a test signal, and a test signal that time-division multiplexes the output signal of the test signal generation circuit into a specific time slot of the transmission data. a data multiplexing and demultiplexing circuit that performs time division multiplexing and demultiplexing of data for received data from the time division multiplexing device in the preceding stage or the relay device in the preceding stage; Each device is equipped with a unique pattern generation circuit that generates a unique pattern for its own repeater, and an arithmetic circuit that performs logical operations on a test signal that is time-division multiplexed with transmission data using the output signal of this unique pattern generation circuit. , the time division multiplexing device on the receiving side includes a reception signal processing circuit that performs signal processing of the reception data from the relay device in the previous stage, and a test signal that separates the test signal time division multiplexed with the reception data. a signal separation circuit; a plurality of pattern generation circuits that generate the same pattern as the unique pattern of each relay device; and a plurality of pattern generation circuits that generate a test signal separated from the received data using the output signal of the pattern generation circuit. It is characterized by comprising an inverse logic operation circuit that performs a logic operation opposite to that performed in .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In the transmission side time division multiplexer 1, a transmission signal processing circuit 10 performs signal processing on transmission data 100, a test signal generation circuit 12 generates a test signal 101, and a test signal multiplexing circuit 11 converts the test signal 101 into transmission data. time-division multiplexing into specific time slots. Each relay device 2A, ~2N
In this case, the data multiplexing/demultiplexing circuit 20 receives the received data 102, .
105, time-division multiplexing and demultiplexing of data;
The unique pattern generation circuits 22a and 22n generate patterns 103a and 103a, 103a and 103a, which are unique to their own repeaters W 2 A and 2N, respectively.
03n, and the arithmetic circuit 21 generates the pattern 103.
A, to 103n are used to perform a logical operation on the test signal time-division multiplexed with the transmission data. In the receiving side time division multiplexing device 3, the received signal processing device 30 performs signal processing on the received data 106 from the preceding relay device 2N, and
~Signal separation circuit 3]7 separates the test signal 108 time-division multiplexed from the received data 106, and pattern generation circuits 32a and ~32n correspond to the unique pattern generation circuits 22a and ~32n in the relay devices 2A and ~2N, respectively. 22n generates the same pattern as the patterns 103a and 103n, and the inverse logic operation circuits 33a and 33n each generate this pattern 103a and 103n.
3a and 103n are used to perform a logical operation on the test signal 107 that is opposite to that of the operation port R21 in each relay device 2A and 2N.

Figure 2 shows an example of the state of the signals at each part in Figure 1.
This is a diagram expressed as ``, which particularly shows the state of time slots in which test signals are time-division multiplexed.

Here, for simplicity, the relay devices are 4 from 2A to 2D.
It is assumed that the exclusive OR is used as the arithmetic circuit 21, 'N ORM' indicates a normal state, and r A L M J is a case of equipment failure in the relay device 2A, which is generally a case of equipment failure. In the case of , the data is all ゛O
’” (or all “1”), so the transmission data 104 (shown in Figure 1) is all “0”.
This example shows the case where the value is fixed to . In Fig. 2, if the relay device 2A is all fixed at 0'° due to equipment failure,
The calculation result with the pattern 103b of the relay device 2B is all I.
IOI+. Therefore, in the receiving side time division multiplexing device 3, the results of any of the inverse logic operation circuits (hereinafter referred to as ALU) 33a to 33d are all "0" or all II I 11
The location of the failure can be detected depending on whether the

〔Effect of the invention〕

As described above, the present invention is effective in not only detecting the presence or absence of a fault in a relay section of a time division multiplex communication system, but also being able to detect where the fault has occurred.

The figure shows an example of the state of the signals at each part in Figure 1.
This is a diagram expressed in ``.

DESCRIPTION OF SYMBOLS 1... Transmission side time division multiplexer, 2A, ~2N... Relay device, 3... Receiving side time division multiplexer, 10... Transmission signal processing circuit, 11... Test signal multiplexing circuit ,1
2... Test signal generation circuit, 20... Data multiplexing/demultiplexing circuit, 21... Arithmetic circuit, 22a, ~22n...
- Unique pattern generation circuit, 30...received signal processing circuit,
31...Test signal separation circuit, 32a, ~32n...
- Pattern generation circuit, 33a, to 33n... Inverse logic operation circuit.

[Brief explanation of the drawing]

Claims (1)

[Claims] In a time division multiplex communication system comprising a plurality of relay devices that relay signals between two time division multiplex devices in multiple stages, the time division multiplex device on the transmitting side includes a transmission signal processing circuit that performs signal processing of transmission data; Each relay device includes a test signal generation circuit that generates a test signal, and a test signal multiplexing circuit that time-division multiplexes the output signal of the test signal generation circuit into a specific time slot of transmission data, A data multiplexing and demultiplexing circuit that performs time division multiplexing and demultiplexing of data received from the time division multiplexing device or the relay device in the previous stage, and a unique pattern generation circuit that generates a pattern unique to each relay device. and an arithmetic circuit that performs a logical operation on a test signal that is time-division multiplexed with transmission data using the output signal of the unique pattern generation circuit, and the time-division multiplexer on the receiving side is connected to the relay device on the previous stage. a received signal processing circuit that performs signal processing of received data from the received data, a test signal separation circuit that separates the test signal time-division multiplexed from the received data, and a pattern that is the same as the unique pattern of each of the relay devices. a plurality of pattern generation circuits that generate a plurality of pattern generation circuits; and an inverse logic operation circuit that uses the output signals of the pattern generation circuits to perform a logical operation opposite to that performed on the test signal separated from the received data. A failure location detection method for a time division multiplex communication system, characterized by comprising: