JPS63146532A - Supervisory equipment for error of transmission line - Google Patents

Abstract

PURPOSE:To use a low speed logic element by supervising a transmission line error through the demultiplexing processing applied to a one-channel signal and using the result as the supervision of transmission line. CONSTITUTION:An input signal (a) is inputted to a demultiplexing circuit 2, from which the demultiplexed one-channel signal is inputted to a frame synchronizing circuit 3. An output of the frame synchronizing circuit 3 is supplied respectively to a parity counter circuit 6 and a parity bit detection circuit 8. The result of the count or detection is inputted to a parity error detection circuit 9. That is, the one-channel signal is demultiplexed from a high speed transmission line signal including plural (n) channels to synchronize in frame. Moreover, the error detection of the one-channel signal is supplied to supervise the transmission line error. Thus, the circuit constitution is realized by a low speed logic element.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to digital multiplex communication. In particular, it relates to error monitoring methods for transmission paths.

〔overview〕

In a monitoring device for a digital multiplex communication transmission line in which a large number of channel signals are time-division multiplexed and transmitted, one channel is taken out, frame synchronized, and this one
By detecting errors in the channel and using the results as the results of monitoring the transmission path, the circuit can be configured as a low-speed circuit and monitoring can be performed at low cost.

[Conventional technology]

A parity check method is an example of a method for detecting code errors in a transmission path. In this parity check method, the transmitting side counts the number of "1"s included in a predetermined number of bits of the data to be sent, and adds that number of odd or even information to the extra parity bits. The receiving side counts the number of "1"s included in a predetermined number of bits, just like the transmitting side.
Errors in the received signal can be detected by comparing the counting results with information obtained from the parity bits. In conventional systems that transmit digital signals via transmission lines, errors in the transmission line are monitored using repeaters installed on the transmission line or terminal equipment installed at the end of the transmission line. .

As shown in Figure 3, the signals of n channels (n is an integer of 2 or more) in which parity bits and frame synchronization bits are inserted for each channel are multiplexed to form a transmission line signal, which is transmitted from the terminal equipment. Sent to the transmission path. When this signal is received by a repeater or receiving end station and a parity check is performed, the transmission line signal is directly applied to the frame synchronization circuit 12 via the signal input terminal 11 as shown in FIG. The taken transmission line signal 13 is applied to a parity counting circuit 15 and a parity bit detection circuit 17.

The parity counting circuit 15 uses the phase information from the frame synchronization circuit 12 to count the number of "1"s included in a predetermined number of bits of the transmission path signal. The parity bit detection circuit 17 uses the phase information from the frame synchronization circuit 12 to detect the parity bit in the transmission path signal and determine its polarity. Parity error detection circuit 18
detects the presence or absence of a parity error using information from the parity counting circuit 15 and the parity bit detection circuit 17.

[Problem that the invention seeks to solve]

In such a conventional parity error detection method, when the transmission line signal is high-speed, most of the frame synchronization circuit 12, parity counting circuit 15, and parity bit detection circuit 17 operate at the clock frequency of the transmission line signal. , and a large number of elements capable of high-speed operation must be used. For this reason, the power consumption of the circuit increases and the operating margin of the circuit also decreases.

SUMMARY OF THE INVENTION The present invention solves the above problems, and aims to provide a transmission path error monitoring device that consumes low power, can be constructed at low cost, and has a sufficient operating margin.

[Means for solving problems]

A first aspect of the present invention is a device for monitoring errors in a transmission line signal in which a large number of channel signals having the same frame synchronization pattern for each channel are time-division multiplexed, in which a channel signal to be monitored is separated from the transmission line signal. a frame synchronization circuit that detects frame synchronization from one channel signal obtained from the output of this demultiplexing circuit; and an error detection circuit that detects errors in the one channel signal according to this frame synchronization. It is characterized by being equipped.

A second invention of the present invention is based on the first invention, wherein the channel signals to be monitored are plural, and a selection circuit is provided for selecting one of the plurality of channel signals and applying it to the input of the frame synchronization circuit. It is characterized by

[Operation] Frame synchronization is achieved by demultiplexing one channel from a high-speed transmission line signal containing a plurality of n channels. Furthermore, errors in the signal □ of that one channel are detected to monitor transmission path errors. As a result, the circuit configuration can be realized using low-speed logic elements, the cost of the circuit can be reduced, and the operating margin can be further improved.

〔Example〕

Next, the present invention will be explained using the accompanying drawings of examples.

FIG. 1 is a block diagram of an apparatus according to a first embodiment of the present invention. FIG. 2 is a signal waveform diagram illustrating the operation of the device shown in FIG. 1. In FIG. 1, the input signal (al) is input to the demultiplexer circuit 2, and the separated one-channel signal is input to the frame synchronization circuit 3. 8
The counting or detection results are input to the parity error detection circuit 9.

FIG. 2(a) shows a waveform of a transmission line signal in which n-channel signals are multiplexed. Here, the frame synchronization pattern of each channel is the same throughout each channel.

This transmission line signal shown in FIG. 2 (al) is applied to the multiplexing/demultiplexing circuit 2 via the signal input terminal 1 shown in FIG.

This demultiplexer circuit 2 has a function of demultiplexing only one channel of the transmission line signal. Here, the separation operation is performed using a 1/n frequency division counter that can be easily configured. Which of the separated channels is to be monitored is determined by the initial phase of the counter. A channel signal of one of the n channels is separated and applied to the frame synchronization circuit 3 of FIG.
Since the frame synchronization bits of each channel are the same, frame synchronization circuit 3 can achieve frame synchronization.

The parity counting circuit 6 counts the parity of the frame synchronization circuit output signal 4 for one channel, which has been synchronized with the frame from the frame synchronization circuit 3, using phase information.

The parity bit detection circuit 8 uses the frame synchronization circuit output signal 7 to detect the parity bit included in the frame synchronization circuit output signal 4. Parity error detection circuit 9 detects parity errors using the outputs of parity counting circuit 6 and parity bit detection circuit 8, similar to the conventional circuit.

Such a circuit enables parity error detection at a speed of 1/n of the transmission line speed. This makes it possible to use logic elements that operate at low speeds, making it easier to reduce power consumption, lower prices, and secure operating margins.

Since the transmission line signal is monitored every n bits in this way, the detection accuracy for burst errors on the transmission line deteriorates, but errors occur almost uniformly on transmission lines using coaxial or optical fiber, so it is practically There is no deterioration in accuracy.

In the device of the first embodiment, by controlling the phase of the 1/n frequency dividing circuit constituting the demultiplexing circuit 2, the channel signal to be monitored can be changed. This phase control is achieved by, for example, the clock signal (
CLK) by dropping one bit at a time. By changing the phase of this 1/n frequency divider circuit according to a constant slow cycle, all channel signals can be sequentially changed.

FIG. 5 is a block diagram of an apparatus according to a second embodiment of the present invention. In this device, a demultiplexing circuit 2 is configured to separate a plurality of channel signals at its output, and a selection circuit 21 for selecting one of the plurality of channel signals is provided to select the selected one channel signal. This is a configuration that supplies power to the frame synchronization circuit 3. The selection circuit 21 is controlled by a selection control circuit 22. Other aspects are the same as those of the first embodiment.

This configuration has the advantage that a general-purpose integrated circuit for multiplexing/demultiplexing circuits can be used as is as the multiplexing/demultiplexing circuit 2 in this system.

The selection control circuit 22 may permanently select one channel signal that is set by chance based on the initial conditions. Also, due to the constant gentle cycle, the demultiplexer circuit 2
It may also be possible to sequentially operate and select a large number of channel signals at the output of the . In this case, the clock signal (CLK) applied to the selection control circuit 22 can be implemented by controlling its phase by, for example, dropping one bit at a time.

Although the parity check method is used as a means of error detection here, the present invention can be similarly implemented using a CRC code or other error detection logic.

〔Effect of the invention〕

As described above, the present invention allows the use of low-speed logic elements by demultiplexing signals of one channel, monitoring transmission path errors, and using this as the transmission path monitoring result. Therefore, it is possible to realize a monitoring system that can reduce power consumption and cost, and also secure a sufficient operating margin.

In the second invention, the demultiplexing circuit is high-speed,
There is an advantage that general-purpose integrated circuit elements can be used.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of a transmission path code error detection device according to a first embodiment of the present invention. FIG. 2 is a diagram of receiving section input signal waveforms and demultiplexing waveforms according to the present invention. FIG. 3 is a transmission line signal waveform diagram in which n-channel signals are multiplexed on the transmitting side. FIG. 4 is a diagram of a transmission path code error detection circuit using conventional parity counting. FIG. 5 is a block circuit diagram of a transmission line code error detection device according to a second embodiment of the present invention. ■, 11... signal input terminal, 2... demultiplexing circuit,
3.12...Frame synchronization circuit, 4.5.13.14
... Frame synchronization circuit output signal, 6.15 ... Parity counting circuit, 7.16 ... Frame synchronization circuit output signal, 8.17 ... Parity bit detection circuit, 9.18
... Parity error detection circuit, 21 ... Selection circuit, 2
2...Selection control circuit.

Claims (3)

[Claims] (1) In a device for monitoring errors in a transmission line signal in which a large number of channel signals having the same frame synchronization pattern for each channel are time-division multiplexed, a demultiplexing circuit (2) for separating the channel signal to be monitored from the transmission line signal is used. ) and a frame synchronization circuit (3) that detects frame synchronization from one channel signal obtained from the output of this demultiplexing circuit.
and an error detection circuit that detects errors in the one channel signal according to the frame synchronization. (2) In a device for monitoring errors in a transmission line signal in which a large number of channel signals having the same frame synchronization pattern for each channel are time-division multiplexed, a demultiplexing circuit (2) that separates the channel signal to be monitored from the transmission line signal is used. ) and a frame synchronization circuit (3) that detects frame synchronization from one channel signal obtained from the output of this demultiplexing circuit.
and an error detection circuit that detects an error in the one channel signal according to the frame synchronization, and the number of channel signals to be monitored is plural, and one of the plurality of channel signals is selected and the frame synchronization circuit detects an error in the one channel signal. 1. A transmission path error monitoring device characterized by comprising a selection circuit that applies the selection circuit to the input of the transmission path error monitoring device. (3) The transmission path error monitoring device according to claim (2), wherein the selection circuit includes means for automatically sequentially switching and selecting one of the plurality of channels to be monitored.