JPS63248238A - Intermediate repeater - Google Patents
Intermediate repeaterInfo
- Publication number
- JPS63248238A JPS63248238A JP8226387A JP8226387A JPS63248238A JP S63248238 A JPS63248238 A JP S63248238A JP 8226387 A JP8226387 A JP 8226387A JP 8226387 A JP8226387 A JP 8226387A JP S63248238 A JPS63248238 A JP S63248238A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- error
- error detection
- sent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims abstract description 21
- 238000012544 monitoring process Methods 0.000 claims description 14
- 238000005259 measurement Methods 0.000 abstract description 20
- 230000005540 biological transmission Effects 0.000 abstract description 9
- 238000000926 separation method Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
Landscapes
- Time-Division Multiplex Systems (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
複数の信号を多重化して伝送するディジタル中間中継器
に関する。特に、ディジタル中間中継器で受信された信
号に含まれる誤りを検出することによりデータの品質を
監視するデータ監視手段に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital intermediate repeater that multiplexes and transmits a plurality of signals. In particular, the present invention relates to data monitoring means for monitoring data quality by detecting errors contained in signals received by digital intermediate repeaters.
本発明は、中間中継器で受信された多重化信号の誤り検
出手段において、
分離された信号を順次ひとつずつ選択して誤り検出する
ことにより、
簡単な構成で確実に誤り検出を実行することができるよ
うにしたものである。The present invention makes it possible to perform error detection reliably with a simple configuration by sequentially selecting separated signals one by one and detecting errors in the error detection means for multiplexed signals received by an intermediate repeater. It has been made possible.
従来のディジタル中間中継器のデータ品質監視手段を第
2図および第3図に示す。Conventional digital intermediate repeater data quality monitoring means are shown in FIGS. 2 and 3.
まず、第2図に示す第一の従来例では、受信回路3に受
信された複数の信号を多重した受信信号lは分離回路4
で各信号に分離される。この分離された信号のうちのひ
とつだけが分岐回路7で分岐され、誤り検出回路12に
接続される。誤り検出回路12で検出された誤りは誤り
計測回路13で計数され、この計測データは監視回路1
4に伝送される。First, in the first conventional example shown in FIG.
is separated into each signal. Only one of the separated signals is branched by a branch circuit 7 and connected to an error detection circuit 12. Errors detected by the error detection circuit 12 are counted by the error measurement circuit 13, and this measurement data is sent to the monitoring circuit 1.
4.
また、第3図に示す第二の従来例では、分離回路4で分
離された受信信号はそれぞれ分岐回路7.8および9で
分岐され、各信号に相当する誤り検出回路12.121
および122および誤り計測回路13.131および1
32にそれぞれ接続される。したがって、分離された信
号ごとに誤り計測が行われ、各信号に対する計測データ
は監視回路14に伝送される。Furthermore, in the second conventional example shown in FIG.
and 122 and error measurement circuit 13.131 and 1
32, respectively. Therefore, error measurement is performed for each separated signal, and measurement data for each signal is transmitted to the monitoring circuit 14.
このように第一の従来例では、分離された信号のうちひ
とつだけの監視を行っているので、他の信号の監視をす
ることができない。例えば、誤り検出回路に分岐されて
いない信号に誤りが発生した場合に、監視回路でこの障
害を監視することができない。また、誤り検出回路に分
岐されている信号に誤りが発生した場合に、伝送路にお
ける誤りであるのか、またはこの信号のみが誤っている
かの判断ができない欠点がある。In this manner, in the first conventional example, only one of the separated signals is monitored, and other signals cannot be monitored. For example, if an error occurs in a signal that is not branched to the error detection circuit, the monitoring circuit cannot monitor this fault. Furthermore, when an error occurs in the signal branched to the error detection circuit, there is a drawback that it is not possible to determine whether the error is in the transmission path or whether only this signal is erroneous.
また、第二の従来例では、分離されたすべての信号につ
いて誤り計測を行うことができるが、誤り検出回路およ
び誤り計測回路が多重化する信号の数だけ必要になり、
回路規模および消費電力の増大を招く欠点がある。In addition, in the second conventional example, error measurement can be performed for all separated signals, but error detection circuits and error measurement circuits are required for the number of signals to be multiplexed.
This has the disadvantage of increasing circuit scale and power consumption.
本発明はこのような欠点を除去するもので、簡単な構成
で確実に誤り検出が行える手段を備えた中間中継器を提
供することを目的とする。The present invention aims to eliminate such drawbacks, and aims to provide an intermediate repeater having a simple configuration and a means for reliably detecting errors.
本発明は、自手段に入力する複数個の信号を多重化する
多重化手段を備えた中間中wE器において、上記多重化
手段への信号の入力経路に個別に挿入された分岐回路と
、この分岐回路で分岐された信号から順次一つの信号を
選択する選択回路と、この選択回路の選択した信号に対
応する分岐回路を識別する識別回路と、上記選択回路の
選択した信号の誤りを検出する誤り検出回路と、上記識
別回路の出力する信号と上記誤り検出回路の出力する信
号とを対応させて監視する監視回路とを備えたことを特
徴とする。The present invention provides an intermediate wE device equipped with a multiplexing means for multiplexing a plurality of signals inputted to the intermediate wE device, including a branch circuit individually inserted into the input path of the signal to the multiplexing means, and A selection circuit that sequentially selects one signal from the signals branched by the branch circuit, an identification circuit that identifies the branch circuit corresponding to the signal selected by the selection circuit, and a detection circuit that detects an error in the signal selected by the selection circuit. The present invention is characterized by comprising an error detection circuit and a monitoring circuit that monitors the signal output from the identification circuit and the signal output from the error detection circuit in correspondence with each other.
中間中継器の分離回路で分離された信号から周期的に1
つの信号を選ぶ。選択された信号と同期をとり信号の分
岐先を識別するとともに、選択された信号の誤りを検出
し、識別出力と誤り出力とを関連づけて監視する。1 periodically from the signal separated by the separation circuit of the intermediate repeater.
Select one signal. It synchronizes with the selected signal, identifies the branch destination of the signal, detects an error in the selected signal, and monitors the identification output and the error output in association with each other.
以下、本発明の一実施例を図面に基づき説明する。 Hereinafter, one embodiment of the present invention will be described based on the drawings.
第1図は、この実施例の構成を示すブロック構成図であ
る。この実施例は、受信回路3と、分離回路4と、多重
化回路5と、送信回路6と、分岐回路7.8および9と
、選択回路10と、信号識別回路11と、誤り検出回路
12と、誤り計測回路13と、監視回路14とを備える
。FIG. 1 is a block diagram showing the configuration of this embodiment. This embodiment includes a receiving circuit 3, a separating circuit 4, a multiplexing circuit 5, a transmitting circuit 6, branch circuits 7.8 and 9, a selection circuit 10, a signal identification circuit 11, and an error detection circuit 12. , an error measurement circuit 13 , and a monitoring circuit 14 .
次に、この実施例の動作を第1図に基づき説明する。複
数の多重化された受信信号1は受信回路3で受信され、
さらに分離回路4で多重化される前の各信号に分離され
る。分離された各信号は分岐回路7.8および9を経由
して、一方は多重化回路5に接続されて多重化され、送
信回路6を経由して送信信号2として伝送路に送出され
る。分岐されたもう一方の信号は選択回路10に接続さ
れ、周期的に選択されてひとつの信号が出力される。Next, the operation of this embodiment will be explained based on FIG. A plurality of multiplexed received signals 1 are received by a receiving circuit 3,
Furthermore, the signal is separated into each signal before being multiplexed by a separation circuit 4. The separated signals pass through branch circuits 7, 8 and 9, one of which is connected to a multiplexing circuit 5 to be multiplexed, and sent out as a transmission signal 2 to a transmission line via a transmission circuit 6. The other branched signal is connected to a selection circuit 10, which periodically selects and outputs one signal.
この信号は誤り検出回路12で誤り検出が行われ、また
選択回路lOと同じ周期で誤り計測回路13で誤りの計
測が行われる。また、選択回路lOの出力は信号識別回
路11に接続され、その信号に含まれているデータから
何番目のデータであるかの識別情仰が抽出され、監視回
路14に送出される。このときの信号の誤り計測データ
も同時に誤り計測回路13を経由して監視回路14に送
られる。An error detection circuit 12 performs error detection on this signal, and an error measurement circuit 13 performs error measurement at the same period as the selection circuit 1O. Further, the output of the selection circuit IO is connected to the signal identification circuit 11, and identification information indicating the number of data included in the signal is extracted and sent to the monitoring circuit 14. The signal error measurement data at this time is also sent to the monitoring circuit 14 via the error measurement circuit 13 at the same time.
すなわち、監視回路では、時分割に各信号の誤り計測デ
ータを監視することができる。したがって、各信号の誤
りデータを独立に処理することができるので、各信号の
品質を独立に監視することができ、伝送路または各信号
回路の障害であるかを容易に判断することができる。That is, the monitoring circuit can monitor error measurement data of each signal in a time-division manner. Therefore, since the error data of each signal can be processed independently, the quality of each signal can be independently monitored, and it can be easily determined whether there is a failure in the transmission path or each signal circuit.
本発明は、以上説明したように、回路規模を大きくする
ことなく多重化された各信号の誤りを一定時間間隔で計
測するので、各信号の品質を独立に監視することができ
る効果がある。As described above, the present invention measures errors in each multiplexed signal at regular time intervals without increasing the circuit scale, and therefore has the advantage that the quality of each signal can be independently monitored.
さらに、各信号ごとに計測した計測データを監視回路に
より平均値処理を行い、信号が分離する前の信号、すな
わち、伝送路の品質も監視することができる効果がある
。Furthermore, the measurement data measured for each signal is subjected to average value processing by the monitoring circuit, and the quality of the signal before the signals are separated, that is, the quality of the transmission path, can also be monitored.
第1図は本発明実施例の構成を示すブロック構成図。
第2図および第3図は従来例の構成を示すブロック構成
図。
1・・・受信信号、2・・・送信信号、3・・・受信回
路、4・・・分離回路、5・・・多重化回路、6・・・
送信回路、7.8.9・・・分岐回路、10・・・選択
回路、11・・・信号識別回路、12.121.122
・・・誤り検出回路、13.131.132・・・誤り
計測回路、14・・・監視回路。FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention. FIGS. 2 and 3 are block configuration diagrams showing the configuration of a conventional example. DESCRIPTION OF SYMBOLS 1... Reception signal, 2... Transmission signal, 3... Receiving circuit, 4... Separation circuit, 5... Multiplexing circuit, 6...
Transmission circuit, 7.8.9... Branch circuit, 10... Selection circuit, 11... Signal identification circuit, 12.121.122
...Error detection circuit, 13.131.132...Error measurement circuit, 14.Monitoring circuit.
Claims (1)
化手段を備えた中間中継器において、 上記多重化手段への信号の入力経路に個別に挿入された
分岐回路と、 この分岐回路で分岐された信号から順次一つの信号を選
択する選択回路と、 この選択回路の選択した信号に対応する分岐回路を識別
する識別回路と、 上記選択回路の選択した信号の誤りを検出する誤り検出
回路と、 上記識別回路の出力する信号と上記誤り検出回路の出力
する信号とを対応させて監視する監視回路と を備えたことを特徴とする中間中継器。(1) In an intermediate repeater equipped with a multiplexing means for multiplexing a plurality of signals input to the intermediate repeater, a branch circuit individually inserted into the input path of the signal to the multiplexing means; a selection circuit that sequentially selects one signal from the signals branched by the selection circuit; an identification circuit that identifies a branch circuit corresponding to the signal selected by the selection circuit; and an error detection circuit that detects an error in the signal selected by the selection circuit. An intermediate repeater comprising: a circuit; and a monitoring circuit that monitors a signal output from the identification circuit and a signal output from the error detection circuit in correspondence with each other.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62082263A JPH0787439B2 (en) | 1987-04-03 | 1987-04-03 | Intermediate repeater |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62082263A JPH0787439B2 (en) | 1987-04-03 | 1987-04-03 | Intermediate repeater |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63248238A true JPS63248238A (en) | 1988-10-14 |
JPH0787439B2 JPH0787439B2 (en) | 1995-09-20 |
Family
ID=13769581
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62082263A Expired - Lifetime JPH0787439B2 (en) | 1987-04-03 | 1987-04-03 | Intermediate repeater |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0787439B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08251128A (en) * | 1995-03-10 | 1996-09-27 | Nec Corp | Multiplex system |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5895445A (en) * | 1981-12-02 | 1983-06-07 | Hitachi Ltd | Tester for digital transmission line |
-
1987
- 1987-04-03 JP JP62082263A patent/JPH0787439B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5895445A (en) * | 1981-12-02 | 1983-06-07 | Hitachi Ltd | Tester for digital transmission line |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08251128A (en) * | 1995-03-10 | 1996-09-27 | Nec Corp | Multiplex system |
JP2870576B2 (en) * | 1995-03-10 | 1999-03-17 | 日本電気株式会社 | Multiplexing method |
Also Published As
Publication number | Publication date |
---|---|
JPH0787439B2 (en) | 1995-09-20 |
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