JPH029370B2 - - Google Patents
Info
- Publication number
- JPH029370B2 JPH029370B2 JP59248111A JP24811184A JPH029370B2 JP H029370 B2 JPH029370 B2 JP H029370B2 JP 59248111 A JP59248111 A JP 59248111A JP 24811184 A JP24811184 A JP 24811184A JP H029370 B2 JPH029370 B2 JP H029370B2
- Authority
- JP
- Japan
- Prior art keywords
- microprogram
- coverage
- logic
- simulation
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59248111A JPS61127042A (ja) | 1984-11-26 | 1984-11-26 | 論理シミユレ−シヨンのテストカバレ−ジ方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59248111A JPS61127042A (ja) | 1984-11-26 | 1984-11-26 | 論理シミユレ−シヨンのテストカバレ−ジ方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61127042A JPS61127042A (ja) | 1986-06-14 |
| JPH029370B2 true JPH029370B2 (cs) | 1990-03-01 |
Family
ID=17173390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59248111A Granted JPS61127042A (ja) | 1984-11-26 | 1984-11-26 | 論理シミユレ−シヨンのテストカバレ−ジ方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61127042A (cs) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01100642A (ja) * | 1987-10-14 | 1989-04-18 | Hitachi Ltd | 計算機システムのテストカバレージ方式 |
| JPH04239338A (ja) * | 1991-01-11 | 1992-08-27 | Nec Corp | マイクロプログラム網羅率測定方式 |
-
1984
- 1984-11-26 JP JP59248111A patent/JPS61127042A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61127042A (ja) | 1986-06-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6523149B1 (en) | Method and system to improve noise analysis performance of electrical circuits | |
| US20030061581A1 (en) | Method of evaluating test cases in a simulation environment by harvesting | |
| JPH06506309A (ja) | 回路シミュレーションインターフェース方法 | |
| CN117785723A (zh) | 动态接口参数关联方法、装置及电子设备 | |
| CN111859985A (zh) | Ai客服模型测试方法、装置、电子设备及存储介质 | |
| CN116048952A (zh) | 一种基于可裁剪ip的实例化模块仿真验证方法及装置 | |
| JPH029370B2 (cs) | ||
| JPH0561931A (ja) | シミユレーシヨン装置 | |
| US20040015792A1 (en) | Method for creating standard VHDL test environments | |
| JP2525393B2 (ja) | 論理シミュレ−ションのテストカバレ−ジ方式 | |
| US6854102B1 (en) | System and method of acquiring delay, setup and hold values for integrated circuit cells | |
| US5937182A (en) | Design verification system using expect buffers | |
| JPH04246778A (ja) | 半導体集積回路の配置方式 | |
| US6965853B2 (en) | Back annotation apparatus for carrying out a simulation based on the extraction result in regard to parasitic elements | |
| US20070073529A1 (en) | Apparatus and method for composite behavioral modeling for multiple-sourced integrated circuits | |
| JPS6339051A (ja) | 論理シミユレ−シヨンのテストカバレ−ジ方式 | |
| US10614181B2 (en) | Electronic design tools using non-synthesizable circuit elements | |
| JPH01100642A (ja) | 計算機システムのテストカバレージ方式 | |
| JPH01156680A (ja) | 論理回路の故障診断方法 | |
| JPS62114040A (ja) | イベントシミユレ−タ | |
| JPH0778195A (ja) | 回路設計cadにおけるデータ更新方式 | |
| JP2669863B2 (ja) | シミュレーション装置 | |
| Yu | VLSI design and CAD technology in Korea | |
| JP3032874B2 (ja) | 等価回路作成方法および論理シミュレーション方法 | |
| JP2003194890A (ja) | 故障解析方法、故障解析支援装置および故障解析支援プログラム |