JPH0291586A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten a test time by inputting the start address (endless address) of a desired firmware program from outside in parallel when a test is conducted, and setting it in an address register in the same way with internal output addresses. CONSTITUTION:When the test is conducted, the start address of the desired firmware program is inputted from outside in parallel through a 1st terminal 21 and set in an address register 16 through a selecting means 22 while handled in the same way with the internal output addresses. Namely, the start address of the firmware program at the time of the testing is inputted and set without any shifting operation unlike before. Consequently, when the device is tested, the start address of the firmware program for realizing a desired operation mode is inputted and set from outside at a high speed.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Field of Industrial Application) This invention provides a firmware memory storing various types of firmware for controlling internal logic operating in various modes, and The present invention relates to an integrated circuit device such as a gate array, which is equipped with a shift register used for serially inputting various data to be given, a start address of a firmware program, etc. from the outside, and is suitable for testing the above-mentioned internal logic.

(Prior Art) Recent integrated circuit devices, such as the gate array shown in FIG.
Built-in OM (firmware memory) 12.

The output data (here, nanoinstructions) of the ROM 12 includes data (control data) for actually controlling the internal logic 11, etc., and a branch destination address. This branch destination address is supplied to the selector 14 together with the output data of the shift register 13 which can be set externally. Selector 14
selects either the branch address from the ROM 12 or the output data of the shift register 13 in response to a select signal 15 from the outside. The selection data of the selector 14 is set in the address register (AR) 1B in synchronization with the clock signal CLK, and specifies the address of the ROM 12.

Now, the gate array (especially the internal logic 11 of FIG. 3)
) can be tested using the following steps.

■ First, the internal logic that should be tested! The start address (entry address) of the nanoprogram corresponding to the operation mode (2) is serially input to the shift register 13 via the serial input line 17.

At this time, the shift enable terminal S of the shift register 13
An active shift enable signal 18 is provided to E.

■ Set the select signal 15 to logic "1" to switch the selector 14, select the entry address that is serially input to the shift register 13 and output in parallel from the shift register 13 in the above (■), and set it in the address register 16. .

(2) The ROM 12 is addressed by the entry address set in the address register 16.

As a result, the nanoprogram data (nanoinstruction) at the designated address position is read out, its control data is supplied to the internal logic 11, and the branch address is supplied to the selector 14. The select signal 15 is a logic “0” except when the entry address is shifted into the shift register 13.
Therefore, the branch address from the ROM 12 is selected by the selector 14 and set in the address register 16, specifying the nanoprogram address to be executed next.As a result, the next nanoprogram data is set to the ROM 12. Read from.

As described above, the nanoprogram specified by the entry address shifted into the shift register 13 is executed, and the internal logic ll in the corresponding operation mode is executed.
will be tested.

(Problems to be Solved by the Invention) As mentioned above, conventionally, in testing integrated circuit devices (internal logic thereof) such as gate arrays that use serial input parallel output shift registers to set external input data, Serially input the start address (entry address) of the firmware program to drive the internal logic in the operation mode to be tested to the above shift register, and then input the start address input to this shift register to the address register of the firmware memory. I needed to set it up. Therefore, in order to start one firmware program, a shift operation is required for the number of bits that constitute the start address (the number of bits that constitute the firmware memory address), and an integrated circuit that applies a firmware memory address with a large number of bits is required. The problem with this device was that it took a long time to test.

Therefore, the problem to be solved by the present invention is to make it possible to input and set the start address of a firmware program for realizing a desired operating mode from the outside at high speed when testing an integrated circuit device.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes a shift register to which various data to be given to internal logic and a start address of a firmware program can be serially inputted from the outside. A desired operation is performed on an integrated circuit device that is configured to select either an input address or an internal output address and set the selected address in an address register to access firmware memory. a first terminal used for external parallel input of a start address of a firmware program in the firmware memory necessary for an internal logic test in mode, and a second terminal used for external control signal input; Select either the start address externally input via the first terminal or the next address to be executed indicated by the read output information from the firmware memory in accordance with the control signal input via the second terminal. At the time of testing, the start address given from the outside via the first terminal is selected and output as the internal output address, set in the address register, and the corresponding firmware program is started, thereby performing the desired operation. The feature is that the internal logic is tested in mode. Further, in the present invention, it is possible to configure the first terminal as a bidirectional terminal and provide an output driver that outputs output information from the firmware memory to the outside from the first terminal in response to a control signal from the second terminal.

(Function) According to the above configuration, during testing, the start address of a desired firmware program is input in parallel from the outside via the first terminal, and is set in the address register via the selection means in the same way as an internal output address. Ru. That is, the input setting of the start address of the firmware program at the time of testing can be performed at high speed without requiring a shift operation, unlike the conventional method. In addition, by making the first terminal a bidirectional terminal and providing an output driver, the output information from the firmware memory is outputted to the outside via the same first terminal except for the start address input period from the first terminal. It can be used for monitoring processing.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

Note that the same parts as in FIG. 3 are given the same reference numerals and detailed explanations are omitted.

FIG. 1 shows a block configuration of a gate array.

In the figure, 21 is a bidirectional terminal used for parallel data input/output with the outside, and 22 is an RO terminal as a nanoprogram memory (or a microprogram memory).
Either the nanoprogram data (nanoinstructions, firmware program data) read from M12 or the data input in parallel from the outside via the bidirectional terminal 21 (here, the entry address of the firmware program in the ROM 12). , is a selector that selects according to a control signal 23 input from the outside. The control data portion (when nanoprogram data is selected) of the selection data of the selector 22 is supplied to the internal logic 11.

24 is an input terminal (control terminal) for the control signal 23, 25 is R
This is a tri-state output driver for externally outputting the nanoprogram data read from the OM 12 from the bidirectional terminal 21 in accordance with the control signal 23.

26 is the address part of the selection data of the selector 22 (branch address when nano program data is selected, entry address when external input data from the bidirectional terminal 21 is selected)
, or the parallel output data of the shift register 13 to an address register (AR) 16 in response to a select signal 15.

The selector 26 differs from the selector 14 in that instead of the branch address in the nanoprogram data from the ROM 12, the address portion of the selection data of the selector 22 is supplied to one input as an internal output address. be.

Next, the operation of the configuration shown in FIG. 1 will be explained.

In the normal state, the state of the control signal 23 (the state of the terminal 24) is 0". In this case, the selector 22
The read data (nano program data) from the ROM 12 supplied to the side input is selected.

The control data included in the nanoprogram data selected by the selector 22 is supplied to the internal logic 11, and the branch address is supplied to the O-side input of the selector 2B. Parallel output data of the shift register 13 is supplied to the 1-side input of the selector 26 .

The selector 2B selectively outputs either the 0-side input data or the 1-side input data to the address register 16 according to the state of the select signal 15 from the outside. Therefore, in this example (control signal 23
is "0"), the operation is similar to the configuration shown in FIG. However, in the configuration shown in FIG. 1, the control signal 23 is "0".
Note that during the period , the newly provided output driver 25 is in an output enabled state and outputs the nanoprogram data from the ROM 12 to the outside via the bidirectional terminal 21.

Next, the operation of the configuration shown in FIG. 1 during a test (test mode) will be explained with reference to the timing chart shown in FIG.

■ When attempting to test especially the internal logic 11 of the gate array shown in FIG.
and input the logic “1° control signal 23 from the outside to terminal 2.
Enter 4.

(2) The entry address (external input address) input in parallel to the bidirectional terminal 21 is supplied to the 1 side input of the selector 22. Also, the logic “1” input to the terminal 24
The control signal 23 is supplied to the selection terminal SL of the selector 22. When the control signal 23 is "1" (therefore 5L-1) as in this example, the selector 22 selects and outputs the first side input data, that is, the entry address input in parallel via the bidirectional terminal 21. While the control signal 23 is "1", the output driver 25 is in an output disabled state, and the state of the bidirectional terminal 21 is prevented from being influenced by the output data of the ROM 12.

(2) The entry address, which is the 1-side input data selected by the selector 22, is supplied to the 0-side input of the selector 2B. A selection terminal SL of the selector 26 is supplied with a selection signal 15 from the outside. This select signal 15 is
At least the test period is set to "0". The selector 26 selects the 0 side input data during the period when the select signal 15 is "0" (SL-0). Therefore, during testing, input is made from the outside to the bidirectional terminal 21, and the selector 2
The entry address supplied to the 0 side input of the selector 2B via the selector 26 is selected by the selector 26. The entry address (external input address) selected by the selector 26 is set in the address register 16 in synchronization with the clock signal CLK, as shown in FIG.

(2) The ROMI 2 is addressed by the entry address set in the address register 1B (input from the outside in parallel via the bidirectional terminal 21).

As a result, the nanoprogram data at the beginning of the corresponding nanoprogram is read from the ROM 12, and the selector 22
and the input of the output driver 25.

(2) Now, after setting the above entry address, the control signal 23 is returned to "0" as shown in FIG. When the control signal 23 is “0°,” the same condition as in the normal state described above occurs.
The selector 22 enters the 0 side input data selection state, and the output driver 25 enters the output enable state. As a result, R
The nanoprogram data (ROM output) from the OM 12 is output to the outside via the bidirectional terminal 21 as shown in FIG. 2 by the output driver 25, and is subject to monitoring operation by a monitor means (not shown). . Further, the nanoprogram data from the ROM 12 is selected by the selector 22, the control data in the data is supplied to the internal logic 11, and the branch address is set to 0 of the selector 22 (same as when inputting the entry address from the outside). supplied to the side input. As described above, the selector 22 selectively outputs the O-side input data to the address register 16 in response to the select signal I5 of logic "0". The branch address in the 0-side input data selected by the selector 26, that is, the nanoprogram data (ROM output) read from the ROM 12, is set in the address register 16 in synchronization with the clock signal CLK, similar to the entry address described above. is,
Specifies the nanoprogram address to be executed next.

(2) The ROM 12 is addressed by the branch and address set in the address register IB.

As a result, the next nanoprogram data is read from the ROM 12 and supplied to the 0 side input of the selector 22 and the input of the output driver 25.

Thereafter, the above steps (1) and (2) are repeated, that is, the nanoprogram designated by the entry address input in a single step from the outside via the bidirectional terminal 21 is executed, and the internal logic 11 is tested in the corresponding operation mode. will be held. Note that the shift register 13 is used to set the entry address in the normal state.

The above description has been made regarding the case where this invention is implemented in a gate array, but this invention also includes a firmware memory storing various types of firmware for controlling internal logic operating in various modes, and various data and firmware provided to the internal logic. The present invention can be applied to any integrated circuit device equipped with a shift register used for serial input such as a program start address.

[Effects of the Invention] As detailed above, according to the present invention, the start address (
Entry address) can be input in parallel from the outside, and this input address can be treated as the internal output address and set in the address register, so the input setting of the start address can be done by shift operation using a shift register like in the past. The test time can be shortened compared to the case where the Further, the output information from the firmware memory can be outputted to the outside via the terminal provided for the parallel input of the start address and provided for external monitoring processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a gate array according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation, and FIG. 3 is a block diagram of a conventional gate array. 11... Internal logic, 12... ROM (firmware memory) 13... Shift register, 14.2
2゜26...Selector, 1B...Address register (AR), 2I...Bidirectional terminal (first terminal), 2
3... Control signal, 24... Input terminal (second terminal),
25...Output driver. ;, 31 National applicant's agent Patent attorney Takehiko Suzue

Claims (2)

[Claims] (1) An internal logic that operates in various modes, a firmware memory that stores various firmware programs for controlling this internal logic, an address register that specifies the address of this firmware memory, and an address that is given to the internal logic. It is equipped with a shift register capable of serial input and parallel output, which is used to serially input various data and the start address of the firmware program, etc. from the outside. In an integrated circuit device that is configured to select one of the output addresses and set the selected address in the above address register, in the test mode, the start address for starting the necessary firmware program is externally set in parallel. A first terminal provided for inputting at least one of the first terminal and either a start address input via the first terminal or an address specified by read output information from the firmware memory is selected as the internal output address. a second terminal for externally inputting a control signal provided at least for controlling the selection operation of the selecting means, and a second terminal for inputting a control signal from the outside through the first terminal in a test mode. An integrated circuit device characterized in that the integrated circuit device is configured to select a start address as the internal output address and set it in the address register to start a corresponding firmware program and test the internal logic. . (2) The first terminal is a bidirectional terminal, and includes an output driver that outputs output information from the firmware memory to the first terminal in accordance with the control signal, and outputs the output information from the firmware memory externally. The integrated circuit device according to claim 1, wherein the integrated circuit device is configured to be monitorable.