JPS6222085A - Test circuit - Google Patents

Abstract

PURPOSE:To test a timer circuit rapidly and accurately whether it is normal or not, by applying a selected common control signal to the timer circuit, and logically processing the counter output by a gate circuit. CONSTITUTION:Data latches 25, 27, 29 are set each with an identical data 'N4b, and a programming is carried out so that timer circuits 26, 28, 30 have an identical frequency dividing. Then, a test mode signal 18 is outputted by the operation of a control input signal 13, and fetches a common input signal 14 to selector circuits 23, 24, 39 to be fed to each of timer circuits 26, 28, 30. If N number of clock pulses are given to the input signal 14, all the timer circuits output a carriage signal simultaneously to a bus 38. At the time, if a fault occurs in any one of the timer circuits 26, 28, 30, no signal is fed to the bus 38, and a fault detection can be possible.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a test circuit for testing a plurality of timer circuits.

BACKGROUND OF THE INVENTION Conventionally, in various control devices, multi-stage counters or timers using frequency dividing circuits have been frequently used to count input pulse signals or to generate a predetermined pulse time or waiting time. There is.

FIG. 3 shows, as an example, a part of a transmitting circuit in a facsimile. In the figure, 1 is a document, VDC is a video controller that receives scan data of document 1, and T
t and Tt are timer circuit units for performing control according to the document size. Further, 5CONT is a scan controller, which includes a reading counter (timer) circuit T and a motor control timer circuit T4.
, Ts - Tb and Tt. VDC is controlled by a random access memory RAM via a data bus, and a line data memory controller DMC is further connected to this data bus. T in this controller
, is a timer circuit section.

Further, CEC is a compaction exchange controller, and includes a timer circuit section T; have.

Although FIG. 3 shows only a part of the transmission side circuit, a transmission controller for transfer and the like is also provided.

In the facsimile circuit as described above, the frequency division number of each timer circuit constituting each timer circuit section T+ -T+o increases depending on the number of bits of the signal to be processed, or the timer itself increases to accommodate multiple functions. The number of types is also increasing. Therefore, when testing each timer circuit, a large amount of input data and testing time are required. That is,
Due to circuit function constraints, for example, the timer circuit of the next block cannot be tested until after the timer circuit of the first block has been tested. However, in conventional testing methods, each timer circuit of each block must be tested in addition. The above-mentioned problem arises because the multiple timer circuits that make up the system are individually tested.

C0 Purpose of the Invention The purpose of the present invention is to provide a timer circuit (or counter circuit)
To provide a test circuit capable of testing accurately in a short time and with a small amount of input data.

20 Structure of the Invention That is, the present invention provides a test mode control circuit that controls a plurality of test modes with one input signal in a test circuit that tests a plurality of timer circuits; a timing generation circuit that is controlled, an input signal selection circuit group that converts a plurality of input signals into one common control signal, and a plurality of input signal selection circuits that are operated in response to each output of the input signal selection circuit group. The present invention relates to a test circuit characterized in that it has a gate circuit group that logically processes each counter output of a timer circuit.

E, Example Examples of the present invention will be described in detail below.

FIG. 1 shows a test circuit for each timer of the circuit as shown in FIG.
7 In FIG. 1, 11 is a test mode control circuit whose state is controlled by a single input signal 13, and each time input i3 changes its state, test mode signal signals 18, 19, 20 . 21 and 22 to control the test status of each part. Reference numeral 12 denotes a timing generation circuit, and the period of the output signals 40, 41, . . . , 14 is controlled by the test mode signal 22.

For example, the speed is increased by the test mode signal 22, and only a specific clock (for example, 14) is output.

Further, 26.2 and 30 are various types of multi-stage frequency division type timer circuits, which constitute each timer circuit section shown in FIG. These timer circuits or frequency divider circuits 26.
28.30 counts the input pulse signals and when a predetermined number is counted, the timer carry signal 32.33
．． 34 respectively. Individual timer circuits typically do not necessarily operate in parallel, but may operate in series with each other. For example, if four 16-bit timer circuits are connected in series, the frequency division number is 262.140.
This requires a huge amount of input data. 25.27
．． A data latch 29 holds data for programming the frequency division number of the timer, and is controlled through the data bus 31.

23.24.39 is a selector for selecting a clock signal to be applied to the timer circuits 26.2B and 30, and when the test mode signal 18 is output, the output 14 of the timing generation circuit 12 is set as one common lock. You will be prompted to enter the information.

35, 36, and 37 are gate circuits that receive the timer carry outputs 32, 33, and 34, perform logical processing (logical product or sum operation), and then connect to the common bus signal line 3.
Output the data to 8. This bus signal line 38 performs a wired 08 function or a wired AND function together with gate circuits 35, 36, and 37.

FIG. 2 explains the operation of the test mode control circuit 11. By changing the state of the input signal tone 3 one after another, the test mode signal 18.22.19
...and controls the test mode. For example, when in test mode (1), test mode signal 1
8 is output, and the input clock of each timer is switched to the common lock input signal by the selector circuits 23, 24, and 39.

Next, the operation of the circuit according to this example will be explained with reference to FIG.

First, the same data "N" is set in the data latches 25, 27, 29, respectively, and the timer circuits 26, 28, .
The block input signal 14 is taken in on the selector circuit 23, 24, and 3 so that 30 has the same frequency division number, and each timer circuit 2
Supply on 6.28.30. Here, the input signal 14 is N
When these clock pulses are applied, carry outputs are simultaneously outputted from all the timer circuits, and a signal is outputted to the bus signal line 38.

At this time, if any one of the timer circuits 26, 28, and 30 malfunctions, no signal is output to the bus signal line 38, so that the defect can be easily detected. Therefore, when testing a plurality of timer circuits, the test circuit according to this example inputs the common clock signal 14, performs logic processing in the gate circuit, and detects this output in three bus signal lines. Since it is possible to immediately determine whether a circuit is normal or abnormal, testing can be performed quickly and accurately (with less input data). For example, in the case of a circuit as shown in FIG. 3, the conventional test method required as much as 5 minutes to test, but it has been confirmed that according to this embodiment, the test can be completed in about 20 seconds.

The test circuit of this example has a normal timer circuit configuration, a test mode control circuit 11, and selectors 23 and 24.
It is only necessary to add gate circuits 35, 39, and 37, and the area surrounded by the dashed line in FIG. 1 is the area to be integrated into an IC. Therefore, as a result of the test, if the timer circuit is normal and put into use, there is no common clock power 14, and the input signals 15, 16, .
17 l.

is input to the selector 23, 24, 39, and each timer circuit 26, 28, 30 is operated.

Although the present invention has been illustrated above, the embodiments described above can be further modified based on the technical idea of the present invention.

For example, the configuration, operation mode, etc. of the test circuit described above may be changed. In addition to the above, the scope of application is also
It is widely applicable as long as it has a timer circuit.

As described above, when testing a plurality of timer circuits, the present invention selects a common control signal and inputs it to the timer circuit, and the output of this counter is logically processed by a gate circuit. Just by detecting this processing result, it is possible to immediately determine whether the timer circuit is normal or abnormal. Therefore, testing can be performed quickly and accurately (with less input data).

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a test circuit according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of a test mode control circuit, and FIG. 3 is a circuit diagram of a part of a device having a timer circuit. In addition, in the reference numerals shown in the drawings, 11-.
2・−・・−・・−・Timing generation circuit 13−・−−
−−−−−−1−−Test mode control signal + 4−−−
−−−−−−−−−−One common lock input signal 15.1
6.17-・----------・--・--・Timer clock signal 18.19.20.21.22--・---------・-Test mode output signal 23.24.
39−−−−−−−−−−−−・Selector (input signal switching circuit) 25.27.2s−・−・−・・−Deaf launch circuit 2
6.28.3o-・--1-------- Timer circuit 32.33.34--------- Timer carry signal 35.36.37----- ----1--Gate circuit 38----- Bus signal line. Agent: Patent Attorney Hiroshi AisakaFigure 1Figure 2Figure 3

Claims (1)

[Claims] 1. In a test circuit that tests multiple timer circuits, there is a test mode control circuit that controls multiple test modes with one input signal, a timing generation circuit whose output cycle is controlled by this test mode control circuit, and multiple timer circuits. Logic processing of each counter output of an input signal selection circuit group that converts an input signal into a single common control signal, and of the plurality of timer circuits that are operated in response to the control signal from the input signal selection circuit group. A test circuit comprising a gate circuit group.