JPH09145792A - Tester for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To test a high speed memory using a low speed circuit by providing an address selection means for supplying an address to an address input terminal, a data selection means for outputting a data to the I/O terminal of memory, a circuit for latching a response signal, etc. SOLUTION: A driver Pin 8 outputs a signal for selecting the output of address selection means and data selection means. Driver pins 9(1)-9(n-1) output latch clocks for data latch circuits 5(1)-5(n-1) and a driver pin 9(n) outputs an output activation signal for a circuit 5. Driver pins 6(1)-6(n) of a tester output a predetermined address data over the entire period of one test cycle. Means 3 controls a signal being outputted through the driver pin 8 such that a data 6 (m) (m=1-n) will appear during an interval T(m) on the output side of the means 3 and that data is delivered to the input Pin of a memory 2 to be measured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device tester, and more particularly to a semiconductor device tester suitable for testing a memory that operates at a higher speed than the operation speed of the tester.

[0002]

2. Description of the Related Art Conventionally, a memory tester has a test pattern generator called ALPG, and the fastest test cycle that the test pattern generator ALPG can generate is the maximum operation speed of the memory tester. .

Therefore, in order to test a high-speed memory that operates at a speed higher than the maximum operating speed, an auxiliary test pattern generator ALPG (Sub ALPG) is added to the main test pattern generator Main ALPG. A method has been generally used in which the tester is operated at an apparent double speed by alternately operating the auxiliary test pattern generator Sub ALPG.

[0004]

However, when the test pattern generator ALPG is added, it is necessary to modify the hardware of the tester, which requires a long construction period and a large capital investment. . Also, in recent years, high-speed memory with operating speed exceeding 100MHz has been developed, and even in the case of a low-speed tester, there was a situation where the speed was insufficient even if ALPG was added.

In view of the above problems, it is an object of the present invention to enable a high speed memory to be tested by a low speed test circuit.

[0006]

A semiconductor device tester of the present invention outputs a plurality of address signals and a plurality of test data corresponding to the plurality of address signals to a memory under test and outputs from the memory under test. In a semiconductor device tester for testing the memory under test by comparing a plurality of response signals to a predetermined expected value, a plurality of address output terminals provided in the tester body for outputting the plurality of address signals. Connected to the address input terminal of the memory under test, select a predetermined address output terminal from the plurality of address output terminals provided on the tester body in a time division manner, and select from the selected address output terminal. Address selection means for outputting the output address to the address input terminal provided in the memory under test, and the plurality of test data In order to output to the memory under test, it is connected to a plurality of data input / output terminals provided in the tester body, and a predetermined data input / output terminal is selected from among the plurality of data input / output terminals in a time division manner. Data selecting means for outputting the data output from the selected data input / output terminal to the data input / output terminal provided in the memory under test, the data input / output terminal on the side of the memory under test, and the plurality of data on the tester side A plurality of latch means provided between the input / output terminal and temporarily holding a plurality of response signals output from the data input / output terminal on the side of the memory under test;
And timing control means for switching the latch timing of the plurality of latch means in synchronization with the time division timing of the address selection means.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION In order to solve the above problems, the present invention employs the following method in order to apparently increase the operating speed of a tester by n times.

That is, n tester driver Pins are assigned to the input Pin of the memory under test, and these drivers are
There is provided a signal time division means for dividing the output of Pin into n for one test cycle and applying them to the input Pin of the memory under test one after another. And the input and output of the memory under test
Similarly, I / O Pins of n testers are assigned to Pins, and n-1 data latch means are provided in addition to the signal time division means.

The input side of the data latch means is commonly connected to the input / output Pin of the memory under test. The output side has 1 to n-1 of the above n I / O pins.
Th connected respectively. The nth I / O Pin is directly connected to the input / output Pin of the memory under test. The output of the memory under test is 1 to n-1 of the test cycle divided into n.
The data output in the second period is sequentially latched by n-1 data latch means.

Then, in the last n-th period, the 1st to (n-1) th I / Os of the testers respectively connected thereto are
Captured by Pin. The data output from the memory under measurement in the n-th period is the input / output Pin of the memory under measurement.
Are directly taken into the nth I / O Pin connected directly to.

As described above, in general, a memory tester can usually output only one pattern of data in one test cycle, and a plurality of response signals output from the memory under test can be compared with an expected value. Basically, it could only be done once in one test cycle.

However, in the method of the semiconductor device tester of the present invention, the tester Pin is used n times as large as one pattern, and as for the output from the tester, n patterns are simultaneously output in one test cycle, and the external signal division is performed. The time-division is performed by means to serially generate data, and the generated serial data is supplied to the memory under test.

Regarding the input to the tester, the data is latched in the data latching means, the data is fetched at one time in the last period of the n time division, and the fetched data and the expected value are collectively compared. The operation speed of the tester can be apparently increased by n times.

Next, one embodiment of the semiconductor device tester of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a memory test system embodying the present invention.
In FIG. 1, 1 is a tester main body, 2 is a measured memory, 3
Reference numerals 4 and 4 are circuits for time-division of signals, 3 is an address selecting unit, and 4 is a data selecting unit. Reference numerals 5 (1) to 5 (n-1) are data latch circuits.

In the tester body 1, an address generating circuit 11 for generating an address signal to be output to the memory under test 2, test data corresponding to the address signal generated by the address generating circuit 11, and the memory under test 2 are generated.
A test circuit 12 for testing the memory under test 2 by comparing a plurality of response signals output from the test circuit 12 with internally generated expected value data, and a data latch circuit 5 (1).
The data acquisition circuit 13 controls the data acquisition timing of up to 5 (n-1), and the timing control circuit 10 controls the overall timing.

The memory 2 to be measured is usually mounted on a normal performance board, a socket board or the like of the tester main body 1. Since there is a space for mounting a load circuit, a relay, etc. on these boards, the address selecting means 3 and the data selecting means 4 can be mounted on the boards. In the present embodiment, the input Pin and the input / output Pin of the memory under test 2 are shown one by one in order to simplify the illustration.

6 (1) to 6 (n) are tester drivers
It is a pin and outputs the address of the memory under test 2. 7
(1) to 7 (n) are I / O Pins of the tester, which exchange data with the memory under test 2 through the address selecting means 3, the data selecting means 4, and the data latch circuit 5.

Reference numerals 8 and 9 denote a driver Pin of the tester. The driver Pin 8 outputs a signal for selectively controlling the output of the address selecting unit 3 and the data selecting unit 4. In addition, drivers Pin 9 (1) to 9 (n-1)
Outputs the latch clock of the data latch circuits 5 (1) to 5 (n-1), and the driver Pin 9 (n) outputs the output activation signal of the data latch circuit 5.

Next, the operation of the semiconductor device tester of the present embodiment constructed as described above will be explained. First, the case of supplying data to the input Pin of the memory under test 2 will be described.
As shown in the test cycle explanatory diagram of FIG.
The test cycle is set to the periods T (1) to T (n).

Tester driver Pins 6 (1) to 6 (n)
Keeps outputting the predetermined address data during the entire period of one test cycle. Then, the signal output through the driver Pin 8 is controlled by the address selecting unit 3, so that 6 (m) (m = 1 to n) data is output from the address selecting unit 3 in the period T (m). And is supplied to the input Pin of the memory under test 2 from the address selecting means 3.

Next, the input / output Pin of the memory under test 2 will be described. The write cycle to the memory under test 2 is exactly the same as the above, and I / O Pins 7 (1) to 7 of the tester are used.
The data supplied from (n) are supplied to the input / output Pin of the memory under test 2 in a time division manner during the test cycles T (1) to T (n).

In the read cycle, the data D (m) (m = 1 to 1) during the period T (m) in the input / output Pin of the memory under test 2 is read.
n) is read out. Therefore, the data fetch circuit 13 sequentially activates the driver Pin 9 (j) by the latch clock in the period T (j), and the data latch circuit 5 is activated.
The data D (j) is sequentially latched to (j). (J = 1 to
n-1)

In the period T (n), the data fetch circuit 13 activates the outputs of the data latch circuits 5 (1) to 5 (n-1) all at once through the driver Pin 9 (n). The latched data D (1) to D (n-1) are taken into the test circuit 12 in the tester 1 from the I / O Pins 7 (1) to 7 (n-1).

At this time, the data D (n) does not come from the data latch circuits 5 (1) to 5 (n-1) but the I / O Pin 7
It is directly incorporated into (n). In the test circuit 12, the data D (1) to D (D) fetched all together during this period T (n).
(N) is compared with the expected value held in the tester,
A defect determination is made.

[0025]

As described above, according to the present invention, the operating speed of the tester can be apparently improved by n times by adding a simple external circuit, and the maximum speed of the tester can be increased. It will be possible to successfully test high speed memories that operate at higher speeds.

[Brief description of the drawings]

FIG. 1 is a block diagram of a memory test system showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a test cycle of the memory test system according to the embodiment.

[Explanation of symbols]

 1 Memory Tester Main Body 2 Memory Under Test 3 Address Selector 4 Data Selector 5 (1) to 5 (n-1) Data Latch Circuit 6 (1) to 6 (n) Tester Driver Pins 7 (1) to 7 ( n) Tester I / O Pin 8 (1) to 8 (n) Tester Driver Pin 9 (1) to 9 (n) Tester Driver Pin

Claims (1)

[Claims] 1. A plurality of address signals and a plurality of test data corresponding to the plurality of address signals are output to a memory under test, and a plurality of response signals output from the memory under test are compared with a predetermined expected value. In the semiconductor device tester for testing the memory under test, a plurality of address output terminals provided on the tester body for outputting the plurality of address signals and an address input terminal of the memory under test are connected. In addition, a predetermined address output terminal is selected from a plurality of address output terminals provided on the tester body in a time division manner,
Address selection means for outputting the address output from the selected address output terminal to the address input terminal provided in the memory under test, and the tester main body for outputting the plurality of test data to the memory under test. It is connected to a plurality of data input / output terminals provided, a predetermined data input / output terminal is selected from the plurality of data input / output terminals in a time division manner, and the data output from the selected data input / output terminal is The data selecting means for outputting to the data input / output terminal provided in the memory under test, the data selecting means provided between the data input / output terminal on the side of the memory under test and the plurality of data input / output terminals on the side of the tester, A plurality of latch means for temporarily holding a plurality of response signals output from the data input / output terminals on the memory side; and a latch type of the plurality of latch means. Tester for a semiconductor device characterized by comprising a timing control means for switching in synchronization with the time division timing of the address selecting means ring.