JPH02895B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an integral type A/D converter constituted by bipolar transistors. [Technical Background of the Invention] Conventionally, this type of A/D converter is configured as shown in FIG. 4, for example. That is, the input terminal 11 to which the analog input voltage AVin is supplied
The cathode of the diode 12 is connected to the anode of the diode 12, and the diode 13 is connected to the anode of the diode 12.
The cathode of is connected. A fixed contact 15a of a switch 15 is connected to the anode of the diode 13, and a power supply is connected via a load resistor 14.
Vcc is connected. One electrode of a capacitor 16 is connected to the movable contact 15b of the switch 15, and the other electrode of this capacitor 16 is connected to a ground point. Further, a constant current source 17 is connected between the fixed contact 15c of the switch 15 and the ground point. The movable contact 15b of the switch 15 is connected to the non-inverting input terminal (+) of a comparator 18, and the inverting input terminal (-) of the comparator 18 is connected to a power supply 19 that generates the reference current Vref1.
The positive terminal of is connected. A ground point is connected to the negative electrode of this power source 19. The output end of the comparator 18 is connected to the input end of a pulse counter 20, and the output end of the pulse counter 20 is connected to the input end of an arithmetic circuit 21. The output of the control circuit 22 controls the switch 15 , the pulse counter 20, and the arithmetic circuit 21, and also supplies the clock signal φ to the pulse counter 20 so that the digital output Dout is obtained from the arithmetic circuit 21. It's getting old. Note that the diodes 12 and 13 charge the capacitor 16 to the level of its forward drop voltage when the analog input voltage AVin is 0V.
High accuracy is achieved by utilizing only the region where the discharge voltage of the capacitor 16 has high linearity. Next, the operation in the above configuration will be explained. First, the output of the control circuit 22 causes the switch 1 to
5 is controlled, and the movable contact 15b is the fixed contact 15a.
When connected to the analog input voltage AVin, the capacitor 16 is charged to a voltage corresponding to the analog input voltage AVin. At this time, the capacitor 16 includes diodes 12 and 13.
A voltage in which the forward direction drop voltage is superimposed is applied. When the charging voltage of the capacitor 16 becomes higher than the reference voltage Vref1 of the power supply 19, the output of the comparator 18 becomes high (“H”) level. next,
The switch 15 is controlled by the output of the control circuit 22, and the movable contact 15b is connected to the fixed contact 15c. As a result, the voltage charged in the capacitor 16 is discharged by the constant current source 17, and the pulse counter 20 starts counting the clock signal φ. When the charging voltage of the capacitor 16 becomes lower than the reference voltage Vref1, the output of the comparator 18 changes from "H" level to low ("L").
Change in level. This change is captured and the counting operation of the pulse counter 20 is stopped. Next, the count value of the pulse counter 20 is supplied to an arithmetic circuit 21, which performs a predetermined arithmetic operation to obtain a digital output Dout. Thereafter, by sequentially repeating the above-described operations, a digital output Dout obtained by A/D converting the analog input voltage AVin is obtained. [Problems in the background art] However, in the above configuration, when the analog input voltage AVin is a negative voltage, the comparator 1
A counter (for example, a one-chip microcomputer) that controls the counting operation by capturing the moment when the output of the comparator 18 changes from the "H" level to the "L" level without the output of the comparator 18 going to the "H" level. The disadvantage is that the simple built-in counter cannot perform normal counting operations. [Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and its purpose is to enable the output signal of the comparator to be counted by the counter even in a region where the analog input voltage is below a predetermined value and cannot be measured. The change from high level to low level is delayed from the start, so that the counting operation of the pulse counter does not become abnormal, and when the analog input voltage is normal, high-precision A/D conversion is possible with the minimum number of components. The purpose of the present invention is to provide an A/D converter that can perform the following steps. [Summary of the Invention] That is, in order to achieve the above object, the present invention provides a clamp for charging a capacitor to a potential higher than the lowest detectable level when the analog input voltage is lower than a predetermined value. It is equipped with a circuit. Another object of the present invention is to provide an A/D converter that can reduce the number of elements by sharing the elements constituting the circuit and is suitable for high integration. [Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In FIG. 1, the same components as those in FIG. 4 are given the same reference numerals. A/ shown in Figure 1
The D converter has three input terminals 23, 11 and 24, and the input terminal 23 has, for example,
0V, input terminal 11 has analog input voltage AVin,
For example, 5V is applied to each input terminal 24. Then, the analog input voltage AVin is A/
By performing D conversion, the conversion accuracy is improved. Each of the above input terminals 23, 11, 24
The bases of PNP-type bipolar transistors 25, 26, and 27 whose collectors are grounded are respectively connected to. These transistors 25, 2
Constant current source 2 is connected to emitters 6 and 27, respectively.
8, 29, and 30 are connected, and the bases of PNP type bipolar transistors 31, 32, and 33 whose collectors are grounded are also connected. Switches 34, 35, and 36 are connected between the emitters of each of the transistors 31, 32, and 33 and the ground point, and are controlled on/off by switch control signals S1, S2, and S3 from the control circuit 22. Further, constant current sources 37, 38, 39 are connected to the emitters of the transistors 31, 32, 33, respectively, and NPN type bipolar transistors 40,
41 and 42 bases are connected. The collectors and emitters of each of the transistors 40, 41, and 42 are connected in common, and the collector connection point and emitter connection point have NPN
The collector and emitter of a type bipolar transistor 43 are connected to each other. The base of this transistor 43 is connected to the positive pole of a power supply 44 that generates a reference voltage Vref2. The transistor 43 and the power supply 44 constitute a clamp circuit, and the reference voltage Vref2 is expressed as "Vref1<Vref2<
The voltage is set to _ΔVBE . In addition, ΔV _BE
is the capacitor 16 powered by the minimum voltage to be measured.
voltage. The emitter of the transistor 43 is connected to the emitter of an NPN bipolar transistor 45 whose collector and base are connected. A switch 47 controlled on/off by a constant current source 46 and a switch control signal S4 from the control circuit 22 is connected between the common emitter connection point of the transistors 43 and 45 and the ground point. Further, the collectors and emitters of NPN type bipolar transistors 48 and 49 constituting a current mirror circuit are connected between the collectors of the transistors 43 and 45 and the power supply Vcc, respectively. The bases of the transistors 48 and 49 are commonly connected, and the collector of the transistor 43 is connected to this base common connection point. A comparator 18 is connected to the base of the transistor 45.
The non-inverting input terminal (+) of is connected, and a capacitor 16 is connected between this non-inverting input terminal (+) and the ground point, and a constant current source 17 and the control circuit 2
Switches 50, which are controlled on/off by a switch control signal S5 from the switch 2, are connected in series. The inverting input terminal (-) of the comparator 18 has a reference voltage
The positive terminal of the power supply 19 that generates Vref1 is connected,
A ground point is connected to the negative electrode of this power source 19. The output end of the comparator 18 is connected to the input end of a pulse counter 20, and the output end of the pulse counter 20 is connected to the input end of an arithmetic circuit 21. This arithmetic circuit 21 is provided with a memory for storing the count output from the pulse counter 20. Then, the output of the control circuit 22 causes the switches 34, 35, 36, 4 to
7, 50, the pulse counter 20, and the arithmetic circuit 21 are controlled, and the pulse counter 20 is supplied with a clock signal φ. and,
The arithmetic circuit 21 obtains a digital output Dout obtained by A/D converting the analog input voltage AVin. Note that the transistors 45, 4
8, 49, constant current source 46, and switch 47,
It is shared by transistors 40 to 43. Next, the operation of the above-described configuration will be explained with reference to the timing chart shown in FIG. At time t1, switch control signals S1 and S5 become "L" level, and switch control signal S4 becomes "H" level (at this time, switch control signals S2, S3 become "H" level).
level is maintained), switches 34 and 50 are turned off, switches 35, 36, and 47 are turned on, and charging of the capacitor 16 with a voltage corresponding to the 0V voltage applied to the input terminal 23 is started. Ru. At this time, the transistor 43 is maintained in an off state. Then, when the charging voltage of the capacitor 16 becomes higher than the reference voltage Vref1 at time t2, the output of the comparator 18 becomes "H" level. At the next time t4, switch control signals S1 and S5 go “H”
When the level S4 becomes "L" level, the constant current source 17 starts discharging the capacitor 16.
Due to this discharge, the charging voltage of the capacitor 16 decreases, and at time t4, when the voltage becomes lower than the reference voltage Vref1, the output of the comparator 18 becomes "L" level. From time t4 when the capacitor 16 starts discharging, to time _t5 when the output of the comparator 18 changes from the "H" level to the "L" level, the count value is supplied to the arithmetic circuit 21 and stored. At the next time t5, the switch control signals S3 and S5 become "L" level, and the switch control signal S4 becomes "H" level (at this time, the switch control signals S1, S5 become "H" level).
2 is maintained at “H” level) and switch 3
6, 50 are off, switches 34, 35, 47
turns on, and the input terminal 2 to the capacitor 16
Charging is started at a voltage corresponding to the 5V voltage applied to 4. At this time, the transistor 43 is maintained in an off state. Then, at time t6, when the charging voltage of the capacitor 16 becomes higher than the reference voltage Vref1, the output of the comparator 18 becomes "H" level. At the next time t7, switch control signals S3, S
5 becomes the "H" level and S4 becomes the "L" level, the constant current source 17 starts discharging the capacitor 16. Due to this discharge, the charging voltage of the capacitor 16 decreases, and at time t8, when it becomes lower than the reference voltage Vref1, the output of the comparator 18 becomes "L" level. From time t7 when the capacitor 16 starts discharging, to time t8 when the output of the comparator 18 changes from "H" level to "L" level.
The count value at the time point is supplied to the arithmetic circuit 21 and stored. At the next time t9, the switch control signals S2 and S5 become "L" level and the switch control signal S4 becomes "H" level (at this time, the switch control signals S1, S
3 is maintained at “H” level) and switch 3
5, 50 are off, switches 34, 36, 47
turns on, and input terminal 1 to capacitor 16
Charging with a voltage corresponding to the analog input voltage AVin applied to 1 is started. At this time, if the analog input voltage AVin is a positive voltage, the off state of the transistor 43 is maintained, and from time t10 to t12, the pulse counter 20 The arithmetic circuit 21 performs a predetermined arithmetic operation to obtain a digital output Dout. On the other hand, when the analog input voltage AVin is a negative voltage, the transistor 41 is turned off, and the capacitor 16 is charged with a voltage corresponding to the reference voltage Vref2.
Since the above reference voltage Vref2 is higher than Vref1, the time when the charging voltage of the capacitor 16 exceeds Vref1
At t10, the output of the comparator 18 becomes "H" level. Then, at time t11, the switch control signal S
2. When S5 becomes "L" level and S4 becomes "H" level, the constant current source 17 starts discharging the capacitor 16. This discharge causes capacitor 16
At time t12' when the charging voltage of Vref1 becomes lower than Vref1, the output of the comparator 18 becomes "L" level. Therefore, when the analog input voltage AVin is a positive voltage,
The output of the comparator 18 is the time as shown by the solid line.
It is at "H" level between t10 and t12, and when the voltage is negative, it is at "H" level between times t10 and t12' as shown by the broken line. Then, the number of clock signals φ during the period from the start of discharging of the capacitor 16 until the output of the comparator 18 changes from the "H" level to the "L" level is counted and stored in the arithmetic circuit 21. A predetermined calculation is performed based on the numerical value and the count value previously stored in the calculation circuit 21 when the input voltage is 0V and 5V, and a digital output is generated.
Get Dout. At this time, by using the A/D conversion data of the input voltages of 0V and 5V as a reference, high precision of the digital conversion output Dout of the analog input voltage AVin is achieved. That is, the count value obtained when the input voltage is 0V is T0, the count value obtained when it is 5V is T5, the count value obtained with the analog input voltage AVin is Tin, and the applied voltage of input voltage 24 is _V24 . Then, Dout=Tin−T0／T5−T0×V ₂₄ . Therefore, according to such a configuration, even if the analog input voltage AVin is a negative voltage, the charging voltage of the capacitor 16 is changed to the inverting input terminal (-) of the comparator 18 by the transistor 43 and the power supply 44.
Since the voltage applied to the capacitor 18 can be set to be higher than the voltage Vref1, the output of the comparator 18 is reliably inverted from the "H" level to the "L" level after the capacitor 16 starts discharging. A/D conversion can be performed using a simple counter. FIG. 3 shows another embodiment of the present invention, in which the A/D conversion is made more precise than the circuit shown in FIG. 1. In Figure 3,
Components that are the same as those in FIG. 1 are designated by the same reference numerals, and detailed explanation thereof will be omitted. That is, the anode of a diode 51 is connected to the common connection point of the bases of the transistors 48 and 49.
The collectors of PNP type bipolar transistors 52 are commonly connected to the cathodes of the transistors 1 and 1. The transistor 52 constitutes a current mirror circuit together with a PNP type bipolar transistor 53, and the collector of the transistor 53 is connected to the base common connection point of the transistors 52 and 53. A transistor 43 constituting the clamp circuit is connected to the collector of each of the transistors 52 and 53.
and the collectors of an NPN type bipolar transistor 54 are connected to each other. The emitters of the transistors 43 and 54 are commonly connected, and a constant current source 55 is connected between the emitter common connection point and the ground point.
A switch 56, which is controlled on/off by a switch control signal S4 outputted from the control circuit 22, is connected in series. The base of the transistor 54 is connected to the non-inverting input terminal (+) of the comparator 18. According to such a configuration, the accuracy of A/D conversion can be further improved. That is, in the circuit shown in FIG. 1, when the analog input voltage AVin is close to the reference voltage Vref2, the on/off status of the transistors 41 and 43 is not completely determined and an error occurs, but as shown in FIG. 3, the transistors 52, 53, By providing a comparator 57 consisting of 43, 54, a power supply 44, a constant current source 55, and a switch 56, the transistors 41, 43 can be turned on/off completely by utilizing the amplification effect of the comparator 57 , resulting in high precision. I can figure it out. [Effects of the Invention] As explained above, according to the present invention, even in a region where the analog input voltage is below a predetermined value and cannot be measured, the output signal of the comparator is changed from high level to low level with a delay from the start of counting of the counter, It is possible to obtain an A/D converter that prevents the counting operation of a pulse counter from becoming abnormal and that can perform highly accurate A/D conversion with a minimum number of elements in the case of a normal analog input voltage.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an A/D converter according to an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the circuit shown in FIG. 1.
FIG. 3 is a circuit diagram for explaining another embodiment of the present invention, and FIG. 4 is a circuit diagram for explaining a conventional A/D converter. 16... Capacitor, AVin... Analog input voltage, Vref1... First reference voltage, 18... Comparator (comparison means), 20... Pulse counter (timekeeping means), 21... Arithmetic circuit (arithmetic means),
Vref2...Second reference voltage.

Claims (1)

[Claims] 1: a first transistor of a first polarity, whose base is supplied with a current corresponding to an analog input voltage and whose collector is connected to a first potential supply source;
The first transistor supplies current to the emitter of the transistor.
current supply means, a first switch means connected between the emitter of the first transistor and the first potential supply source, and a second polarity switch means, the base of which is connected to the emitter of the first transistor. a second transistor, a third transistor of a second polarity, the emitter of which is connected to the emitter of the second transistor, and the collector of which is connected to the collector of the second transistor; a reference voltage generating means for providing a reference voltage of 1; a base is supplied with a current corresponding to a first input voltage serving as a reference during A/D conversion; and a collector is connected to the first potential supply source. a fourth transistor of a first polarity; a second current supply means for supplying current to the emitter of the fourth transistor; and a fourth transistor connected between the emitter of the fourth transistor and the first potential supply source. a second switching means; a second polarity transistor having a base connected to the emitter of the fourth transistor, a collector connected to the collector of the third transistor, and an emitter connected to the emitter of the third transistor; a sixth transistor of first polarity, the base of which is supplied with a current corresponding to a second input voltage serving as a reference for A/D conversion, and the collector of which is connected to the first potential supply source; a transistor, a third current supply means for supplying current to the emitter of the sixth transistor, and a third switch means connected between the emitter of the sixth transistor and the first potential supply source; a seventh transistor of second polarity, the base of which is connected to the emitter of the sixth transistor, the collector of which is connected to the collector of the third transistor, and the emitter of which is connected to the emitter of the third transistor; a second transistor whose bases are commonly connected and whose emitters are connected to the emitters of the third transistor;
an eighth transistor of polarity, and the second, third,
a current mirror circuit that supplies current from a second potential supply source to the collectors of the fifth, seventh, and eighth transistors; and a current mirror circuit that has one end connected to the common emitter connection point of the third and eighth transistors. a fourth switch means provided between the other end of the first current source and the first potential supply source; a base of the eighth transistor and the first potential supply source; a second current source having one end connected to the base of the eighth transistor; and between the other end of the second current source and the first potential supply source. a fifth switch means provided; a comparison means for comparing the charging voltage of the capacitor with a second reference voltage; and a comparison means for comparing the charging voltage of the capacitor with a second reference voltage; a clock means for measuring the time until the voltage drops to the reference voltage No. 2; a calculation means for obtaining a digital signal based on the output of the clock means; and the first to fifth switch means, the clock means, and the calculation means. A/D control means for controlling the analog input voltage based on the A/D conversion values of the first and second input voltages.
A D conversion value is obtained, and the first reference voltage is higher than the second reference voltage, and is lower than the voltage of the capacitor charged with the lower input voltage of the first and second input voltages. A/ characterized by low
D converter. 2 a first transistor of a first polarity whose base is supplied with a current corresponding to an analog input voltage and whose collector is connected to a first potential supply source;
The first transistor supplies current to the emitter of the transistor.
current supply means, a first switch means connected between the emitter of the first transistor and the first potential supply source, and a second polarity switch means, the base of which is connected to the emitter of the first transistor. a third transistor of a first polarity, the base of which is supplied with a current corresponding to a first input voltage serving as a reference for A/D conversion, and the collector of which is connected to the first potential supply source; a second current supply means for supplying current to the emitter of the third transistor; and a second current supply means connected between the emitter of the third transistor and the first potential supply source.
switching means, the base of which is connected to the emitter of the third transistor, and the collector of which is connected to the emitter of the third transistor;
A fourth transistor of a second polarity whose emitter is connected to the emitter of the second transistor is connected to the collector of the transistor, and a fourth transistor of a second polarity whose emitter is connected to the emitter of the second transistor is connected to the collector of the transistor. a fifth transistor of a first polarity to which a current is supplied and whose collector is connected to the first potential supply source; a third current supply means for supplying current to the emitter of the fifth transistor; a third switch means connected between the emitter of the fifth transistor and the first potential supply source; a third switch means having a base connected to the emitter of the fifth transistor;
a sixth transistor of a second polarity, the collector of which is connected to the collector of the second transistor, and the emitter of which is connected to the emitter of the second transistor; a seventh transistor of a second polarity connected to the emitter of the transistor, and a first current mirror that supplies current from a second potential supply source to the collectors of the second, fourth, sixth, and seventh transistors, respectively. a circuit, a first current source having one end connected to a common emitter connection point of the second, fourth, sixth and seventh transistors, and the other end of the first current source and the first potential; a fourth switching means provided between the supply sources; a reference voltage generating means for outputting the first reference voltage; and an eighth transistor of a second polarity, the output terminal of the reference voltage generating means being connected to the base. , a ninth transistor of a second polarity whose emitter is commonly connected to the emitter of the eighth transistor and whose base is connected to the base and collector of the seventh transistor;
a second current mirror circuit that supplies current from a second potential supply source to the collectors of the eighth and ninth transistors; the anode is connected to one output end of the first current mirror circuit; the cathode is a diode connected to the collector of the eighth transistor; a second current source having one end connected to a common emitter connection point of the eighth and ninth transistors; a fifth switch means provided between the first potential supply source; a capacitor connected between the base of the seventh transistor and the first potential supply source; a third current source to which one end is connected; a sixth switch means provided between the other end of the third current source and the first potential supply source; a comparison means for comparing the voltage with a reference voltage of the second reference voltage, and a timer for measuring the time from the start of discharging of the capacitor until the charging voltage of the capacitor decreases to the second reference voltage based on the output of the comparison means; A calculation means for obtaining a digital signal based on the output of the time measurement means, and a control means for controlling the first to sixth switch means, the time measurement means, and the calculation means, the control means for controlling the first to second input voltages. The A/D conversion value of the analog input voltage is based on the A/D conversion value of
A D conversion value is obtained, and the first reference voltage is higher than the second reference voltage, and is lower than the voltage of the capacitor charged with the lower input voltage of the first and second input voltages. A/ characterized by low
D converter.