JPS6149856B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Background of the Invention The present invention relates to an analog-digital (A-D) conversion circuit used, for example, in measurement control.

Technical background of the invention and its problems Generally, when configuring an A-D converter, D
-A comparison circuit based on the A converter is used. In such a circuit, A-D
The accuracy of the converter is determined by the accuracy of the DA converter and the offset voltage of the comparator. Therefore, it is necessary to improve the accuracy of the DA converter and comparator. However, when this circuit is made monolithic, special processes such as trimming are required to improve the accuracy of the DA converter, which has the disadvantage of impairing mass production and increasing costs.

FIG. 1 shows a differential slope type integral AD converter circuit that can eliminate the above-mentioned drawbacks, and is constructed using an integrator that can easily provide a relatively high-precision output. In the figure, 11 is an integrator, 12
is a zero cross comparator, 13 is a binary counter, S ₁ and S ₂ are switches, R ₁ and R ₂ are resistors, and D
is a diode, C is a capacitor, D _z is a Zener diode, NOT ₁ , NOT ₂ inverter, B ₁ , B ₂
is a driver, NAND is a NAND gate, v ₁ is an analog input voltage, V _ref is a reference voltage, C _p is a clock pulse, R _p is a reset pulse, and D _OUT is a digital output.

Next, the operation of the AD converter shown in FIG. 1 will be explained. The switches S ₁ and S ₂ are driven to the on or off state by the signal of the maximum digit an of the binary counter 13. This A-D converter is
First, the analog input voltage v ₁ is integrated by the integrator 11 for an initial fixed period of time, and then discharged by the constant current (V _ref /R ₁ ) circuit. Since this discharge time is proportional to the input voltage _v1 , by counting the clock pulses _Cp during this time, the digital output _DOUT
This is what you get.

However, such a configuration has the disadvantage that the delay of the zero cross converter 12 causes errors and that it is difficult to increase the conversion speed.

Purpose of the Invention This invention was made in view of the above circumstances, and its purpose is to provide an analog-to-digital conversion circuit that does not require special technology and is capable of highly accurate and high-speed operation. It is to be.

Summary of the Invention That is, in this invention, the output of an integrator that obtains an integral slope from a level lower than the ground potential by switching a switch is supplied to first and second comparators, and this output is supplied to the first comparator. A second comparator compares the voltage with a ground potential and an analog input voltage, and supplies the outputs of the first and second comparators to a binary counter via a control circuit including an oscillator.
Counting of clock pulses is started when the output of the integrator reaches the ground potential, and the counting operation is stopped when the clock pulse matches the analog input voltage, and the count value during this period is obtained as a digital output.

Embodiment of the Invention An embodiment of the invention will be described below with reference to the drawings. Figure 2 shows its configuration.
A voltage divided into a predetermined voltage by a resistor R connected between the power supply VR and the ground is supplied to the inverting input terminal (-) of the integrator 14 via a switch _SW1 and a resistor R _I. Here, the resistor R is a variable resistor, and is appropriately set according to the scale of the integral output. The non-inverting input terminal (+) of the integrator 14 is connected to ground or the power supply via a switch _SW3 . A capacitor C _I and a switch SW ₂ are connected in parallel between the output terminal of the integrator 14 and the inverting input terminal (-). The switches SW ₂ and SW ₃ are supplied with a conversion command signal STC to perform on-off control, and this signal STC is supplied to the switch SW ₁ via an inverter NOT. The output signal INT _OUT of the integrator 14 is supplied to a first comparator 15 whose one input terminal is grounded, and
It is supplied to a second comparator 16, one input of which is supplied with the analog input signal A _IN . Output C of the first and second comparators 15 and 16
_10UT and _C2OUT are supplied to monostable multivibrators 17 and 18, respectively, and then supplied to a flip-flop circuit 19 consisting of NOR gates _NOR1 and _NOR2 in synchronization with the output pulse of the oscillator OSC. The input terminal of the above NOR gate NOR ₂ has a conversion command signal.
STC is supplied and its output CE is connected to the oscillator at one end.
The clock pulse is supplied from the OSC to the AND gate AND. The clock pulse CK corresponding to the analog input output from this AND gate AND is counted by a binary counter 20 to obtain a digital output _DOUT .

The operation of the above configuration will be explained using the timing chart shown in FIG. When the conversion command signal STC becomes high level, switch SW ₁ is turned off, SW ₂ is turned on, the contact of SW ₃ is connected to the side, and the output signal INT _OUT of the integrator 14 becomes a level lower than the contact potential GND. . At the same time, the binary counter 20 is reset. next,
When the conversion command signal STC returns to low level, the switch SW ₁ is turned on, the switch SW ₂ is turned off, and the movable contact of SW ₃ is connected to the ground point GND side, and a positive slope integration is performed. Then, the integrator 1
When the level of the output INT _OUT of the comparator 15 becomes the ground potential GND, the output C _1OUT of the comparator 15 is inverted,
This output _C1OUT causes the monostable multivibrator 17 to generate a pulse for a predetermined time. The trigger pulse generated from the multivibrator 17 inverts the flip-flop circuit 19 and causes the binary counter 20 to start counting. Next, when the level of the output INT _OUT of the integrator 14 reaches the level of the analog input voltage A _IN , the output C _2OUT of the comparator 16 is inverted, and a trigger pulse is generated from the monostable multivibrator 18 by this inverted output. Flip-flop circuit 19
is inverted, and the counting operation of the binary counter 20 is stopped. Then, the count value of the binary counter 20 is obtained as a digital output.

In such a configuration, the difference in delay between the first and second comparators becomes an error voltage. The first and second comparators mentioned above are manufactured in the same process, so they have the same characteristics, and there is almost no difference in delay between the comparators, so high precision can be achieved, and the discharge time in the circuit shown in Figure 1 is unnecessary. High-speed operation is possible.

Effects of the Invention As explained above, according to the present invention, it is possible to obtain an analog-to-digital conversion circuit that does not require special techniques such as trimming, can be mass-produced easily and at low cost, and is capable of high precision and high-speed operation. It will be done.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional dual slope type integral A-D converter circuit, FIG. 2 is a diagram showing an analog-to-digital converter circuit according to an embodiment of the present invention, and FIG.
The figure is a timing chart of the circuit shown in FIG. 2 above. 14... Integrator, 15, 16... Comparator, 20... Binary counter, OSC... Oscillator, STC... Conversion command signal, A _IN ... Analog input signal, D _OUT ... Digital output signal, GND... Ground potential.

Claims (1)

[Claims] 1 an integrator, and an integrator provided at the inverting input terminal of the integrator and controlling supply or non-supply of a reference voltage to the inverting input terminal of the integrator by controlling switching based on the inverted signal of the conversion command signal. and a second switch provided at the non-inverting input terminal of the integrator and controlled by switching based on the conversion command signal to control the supply of negative voltage or ground voltage to the non-inverting input terminal of the integrator. a third switch connected between the output terminal and the inverting input terminal of the integrator and controlled by switching based on the conversion command signal; a first comparator that compares the output level of the integrator with a ground voltage, a second comparator that compares the output level of the integrator with an analog input signal level; first and second monostable multivibrators each supplied with the output of the second comparator and operated in synchronization with the output pulse of the oscillator;
A flip-flop that is set or reset by the outputs of the first and second monostable multivibrators and controlled by the conversion command signal, and a counter that counts the AND output of the output of the flip-flop and the output pulse of the oscillator. An analog-to-digital conversion circuit comprising: the counter, and obtaining an analog-to-digital conversion output from the counter.