JPH0288247U - - Google Patents

Info

Publication number
JPH0288247U
JPH0288247U JP16720288U JP16720288U JPH0288247U JP H0288247 U JPH0288247 U JP H0288247U JP 16720288 U JP16720288 U JP 16720288U JP 16720288 U JP16720288 U JP 16720288U JP H0288247 U JPH0288247 U JP H0288247U
Authority
JP
Japan
Prior art keywords
sealing resin
resin
exposed
semiconductor device
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16720288U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16720288U priority Critical patent/JPH0288247U/ja
Publication of JPH0288247U publication Critical patent/JPH0288247U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ａは、本考案の第１の実施例を示す内部
端子構造図、第１図ｂは、その外形図、第２図は
第２実施例を示す外形図、第３図ａは、第２の実
施例におけるシヨート状態を示す断面図、第３図
ｂは、第２実施例における使用状態を示す断面図
、第４図ａは、従来例を示す内部端子構造図、第
４図ｂは、その外形図である。 １……チツプ（ＭＯＳ ＦＥＴ）、２……放熱
板、３，４……ボンデイングワイヤ、５，６……
外部リード、７，８……表面部露出端子、９……
封止樹脂部、１０……断線用穴、１１……金属線
。 FIG. 1a is an internal terminal structure diagram showing the first embodiment of the present invention, FIG. 1b is an outline diagram thereof, FIG. 2 is an outline diagram showing the second embodiment, and FIG. 3a is FIG. 3b is a sectional view showing the shot state of the second embodiment. FIG. 4a is a sectional view showing the internal terminal structure of the conventional example. FIG. 4b is its outline drawing. 1... Chip (MOS FET), 2... Heat sink, 3, 4... Bonding wire, 5, 6...
External leads, 7, 8... surface exposed terminals, 9...
Sealing resin part, 10...hole for disconnection, 11...metal wire.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 樹脂封止型半導体装置において、封止樹脂内部
で外部リードの一部が伸延して、封止樹脂表面に
露出して設けられていることを特徴とする半導体
装置。 1. A resin-sealed semiconductor device, characterized in that a portion of an external lead extends inside the sealing resin and is exposed on the surface of the sealing resin.
JP16720288U 1988-12-23 1988-12-23 Pending JPH0288247U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16720288U JPH0288247U (en) 1988-12-23 1988-12-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16720288U JPH0288247U (en) 1988-12-23 1988-12-23

Publications (1)

Publication Number Publication Date
JPH0288247U true JPH0288247U (en) 1990-07-12

Family

ID=31455283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16720288U Pending JPH0288247U (en) 1988-12-23 1988-12-23

Country Status (1)

Country Link
JP (1) JPH0288247U (en)

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