JPH0285935A - Data processor and its debugging device - Google Patents

Abstract

PURPOSE:To improve the debugging efficiency of the data processor by using a control terminal which stops the working of only a CPU and another control terminal which stops the entire working of the data processor. CONSTITUTION:A single chip microcomputer 20 for emulation contains a processor stop terminal PBRK which stops the working of only an internal processor and a system stop terminal SBRK which stops the entire working of a system. Thus the microcomputer 20 can stop the working of the processor only or the entire system working in accordance with the setting state of a register 26. As a result, it is possible to check the state of the processor with the working of a peripheral logic continued as it is or to stop the entire working of the microcomputer 20 via the system break to check the entire state of the system. In such a constitution, the debugging efficiency is improved for a data processor.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a technology that is particularly effective when applied to microcomputers and their debugging tools, for example, to single-chip microcomputers and in-circuit emulators for their evaluation. It is about effective techniques.

[Prior Art] In the development of microcomputer application equipment, in-circuit emulators are used to debug the application system and perform detailed evaluation of the system. As shown in FIG. 2, such an in-circuit emulator 2 is connected between a system development device 1 such as a parent computer (host computer) for software development and an application device 3 under development, and is connected to the application device 3 under development. It acts as a debugger while also acting as a debugger to support detailed system debugging.

Conventional in-circuit emulators include a slave microcomputer for emulation that performs the functions of the target microprocessor, an emulation control unit to implement emulation and various debugging functions, and settings for stopping conditions for program execution and tracing. , breakpoint control unit that stops the program or trace when a condition is met, trace memo 5.
It has a built-in memory section, a substitute memory section that is lent out when the application equipment (user system) has no memory available, and a master microprocessor for controlling these sections. (Refer to rLSI Handbook Jp562 to p563, published by Ohmsha on November 30, 1980).

In such an in-circuit emulator, a plug at the end of a cable 4 extending from the main body is connected to a socket 5 for the target microprocessor provided in the application equipment, so that the slave microcomputer can be connected to the target microprocessor. It has an emulation function that performs functions on behalf of the computer. Furthermore, there is a real-time trace function that samples various data and status signals in real time during emulation execution and stores them in the trace memory section, and virtually stops the control operation of applied equipment by the emulation microcomputer. It is equipped with various debugging functions such as a break function.

[Problems to be Solved by the Invention] The break function in the conventional emulator for single chip microcomputers has the following problems. In other words, it was unclear whether the break condition was a break for the program from the programmer's perspective or a break for other logic. Therefore, the break function has been implemented in various ways, such as a stop function for only a central processing unit (hereinafter simply referred to as a processor), or a stop function for the entire single chip microcomputer. Therefore, for example, if we consider a break when a DMA (direct memory access) controller inside a single chip microcontroller is performing a DMA transfer between memories I10, the break is a stop function based on the processor's program execution conditions. In this case, only the processor breaks and the DMA controller continues functioning.

In this case, even if the user wants to know the entire status of the single chip microcomputer at the time of the break.

That would not be possible since the DMA controller would not stop functioning. On the other hand, if the break function is to stop the entire microcontroller, the entire single chip microcontroller will stop operating at the time of the break, so the DMA transfer between the memories 170 will not be guaranteed and data will not be destroyed. and the user needs to reconstruct the corrupted data.

In this way, no matter which method is used, the functionality is limited for the user.

The present invention was made by focusing on the above-mentioned problems, and the break function is divided into breaks for programs seen from the programmer (hereinafter referred to as processor breaks) and breaks for other logic (hereinafter referred to as system breaks). The purpose of this invention is to provide an emulator that can greatly improve the debugging efficiency of systems using single chip microcontrollers.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In other words, by providing a single-chip microcontroller with a terminal for stopping only the processor and a terminal for stopping the entire system, a register for setting a processor break or a system break, and its settings can be used to send a processor break signal or system break to a single-chip microcontroller. It has a circuit that supplies a break signal and a circuit that detects the state of the emulation path and generates a break source signal when a break condition (for example, the value of the program counter matches the set value) is met. It is.

[Operation] According to the above means, the type of break can be distinguished by the register for setting a processor break and a system break, and the logical product of the signal sent from the break generation circuit and the output of the above-mentioned register is used. By taking , either the processor break signal or the system break signal is selected, and the selected signal is applied to the processor stop terminal or the system stop terminal of the single chip microcomputer. This allows the single chip microcontroller to control the processor only, depending on the register settings.
Or the whole thing will be stopped.

Embodiment FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to an in-circuit emulator.

In the figure, reference numeral 20 denotes an emulation single-chip microcomputer that controls the operation of the user system, that is, emulates it, by substituting the functions of the microcomputer included in the user system to be debugged.

This emulation single-chip microcomputer 2o has a processor stop terminal PBRK that can stop only the internal processor, and a system stop terminal 5BRK that can stop the entire operation. A bus monitoring circuit 23, a trace buffer memory 24, and a break memory 25 are connected via an emulation bus 22. Note that the user system is a CPU for emulation.
20 is connected to the emulation bus 22 during emulation, and is disconnected from the emulation bus 22 during break. Here, the emulation bus is a bus on which signals indicating the internal state of the single chip microcomputer are carried.

The emulation bus during emulation includes a bus cycle monitoring circuit 23, a trace buffer memory 24,
It is monitored by break memory 25. That is, the logical conditions for breaking depending on the emulation state are set in the monitoring circuits 23, 24, and 25, respectively.

The break memory 25 uses RAM, and if you write "1" in the address location where you want to stop the program, when that address signal is output on the bus, "1" will be read out, and this will be used as the break source signal. be able to.

The bus cycle monitoring circuit 23 monitors the state of the emulation bus and generates a break source signal BSI when the bus enters a parity error state, for example. Further, the trace buffer memory 24 has a built-in address counter,
A break source signal BS2 is generated when the trace content exceeds the memory capacity. Furthermore, break memory 25
A break condition is set so that a break source signal BS3 is generated when the state of the emulation bus, for example, the address signal indicates a certain value.

The emulator of this embodiment also includes a processor break/system break setting register 26 that can be set by the host computer, and each of the bus monitoring circuits 23 and
24. When the break source signals BSI to BS3 are supplied from 25, the break signal generation circuit 2 generates the break signal BRK at an appropriate timing that matches the bus cycle.
7 and the generated break signal BRK to the above register 2.
a gate circuit 28a for supplying a signal to the emulation single-chip microcomputer 20 according to the setting state of 6;
28b is provided.

In this embodiment, the register 26 is composed of 2 bits, and depending on the setting state, for example, if it is #l or QI+, a break signal BRK is supplied to the system stop terminal 5BRK.
l(Q, Ql'', break signal BR to any terminal
It is configured to control the gates 28a and 28b so as not to input K.

In the emulator of this embodiment, before executing emulation, the break register 26 is first set to determine whether the processor is to be stopped or the entire system is to be stopped when a break condition is satisfied during emulation. Then, during execution of emulation, when a signal on the emulation bus 22 matches a break condition, a break source signal BS3 is sent from the break memory 25 or the like to the break signal generation circuit 27.

Upon receiving this break source signal, a break signal generating circuit 27 forms and outputs a break signal BRπ at an appropriate timing. This signal depends on the setting state of the register 26.
It is supplied to either the processor stop or system stop terminal of the single-chip microcomputer 20 for emulation. In the case of a processor break, only the processor stops, and the peripheral I10 such as the DMA controller
Operation of the device continues. Therefore, the emulator user can see the state of the processor.

Furthermore, for example, if a processor break condition is met and the processor stops operating while the DMA controller inside the single chip microcontroller is loading data from the floppy disk device, data loading from the floppy disk device will continue. be done. This prevents data from being destroyed due to the stoppage of the DMA controller when a break occurs, eliminates the need for data reconstruction, and improves debugging efficiency.

In addition, when the processor is controlling the peripheral I10 device using a program, if you want to see both the state of the processor and the state of the peripheral I10 device at the time of the break, register the break signal BRK so that it is input to the system terminal. If 26 is set, the operation of the entire single-chip microcomputer can be stopped, thereby improving debugging efficiency.

In the above embodiment, the processor break/system break setting register 26 is composed of 2 bits.
It consists of a 1-bit flag, and its output signal is supplied as is to the control terminal of one gate 28a (or 28b), and the inverted signal is supplied as a control signal to the other gate 28b (or 28a) via an inverter. Just do it.

Further, in the embodiment, the host CPU sets the conditions to the processor break/system break setting register 26, but the register 26 may also be set by the emulation CPU 20.

As explained above, in the above embodiment, the single-chip microcontroller is provided with a terminal for stopping only the processor and a terminal for stopping the entire processor, and
Depending on the register that sets the system break and its settings, the circuit that supplies the processor break signal or system break signal to the single chip microcontroller and the state of the emulation bus are detected, and the break source is detected when the processor break condition is met. Since a signal generating circuit is provided, either the processor break signal or the system break signal is selected, and the selected signal is applied to the processor stop terminal or the system stop terminal of the single chip microcomputer.

As a result, the single chip microcontroller will be able to stop only the processor or the entire processor depending on the register setting state, which has the effect of greatly improving the debugging efficiency of systems using the single chip microcontroller. be.

Additionally, the two break terminals provided on the single-chip microcontroller can be used to stop the operation of a desired circuit section during operations other than emulation, which has the effect of strengthening the functionality of the single-chip microcontroller. There is also.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, the emulation single-chip microcontroller of the embodiment has two break terminals, and by inputting a break signal to either one, it is possible to stop only the processor or stop the entire processor. As described above, the single-chip microcomputer may be configured so that only the peripheral I10 device is stopped when a break signal is input to both terminals. In that case, for example, register 2
By setting "1.1" to 6, the break signal BRK generated by the break signal generation circuit 27 can be input to the two break terminals of the single-chip microcomputer.

The above explanation has mainly been about the application of the invention made by the present inventor to a single-chip microcomputer and its emulator, which is the background field of application. It can be used for microcomputers with logic circuits and their depacking tools.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, according to the present invention, debugging efficiency can be greatly improved by allowing the peripheral logic to continue operating as it is and checking the status of the processor, or by using a system break to stop the entire single-chip microcontroller and checking the status of the entire system. be able to.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to an in-circuit emulator for a single-chip microcomputer. FIG. 2 is a block diagram showing the overall configuration of a system development apparatus to which an in-circuit emulator according to the present invention is applied. 20...Single-chip microcomputer for emulation, 26...Break setting register, 27...
Break signal generation circuit, 23...Bus cycle monitoring circuit, 24...Trace buffer memory, 25...
...Break memory.

Claims (1)

[Scope of Claims] 1. In a data processing device including a central processing unit and a logic section provided around the central processing unit, a control terminal for stopping only the operation of the central processing unit and stopping the operation of the entire device 1. A data processing device, comprising: a control terminal for controlling the data processing device. 2. bus monitoring means for monitoring the state of the bus and detecting the establishment of a break condition; break signal generation means for generating a break signal to the control terminal when the break condition is satisfied; A debugging device characterized by comprising registers or flags for supplying or setting.