JPH0283777A - Repetitive addition circuit - Google Patents

Abstract

PURPOSE:To realize a high-speed operation with a simple circuit constitution by storing the addition data outputted successively from an accumulating device into an FIFO device in an FIFO way and therefore carrying out successively the FIFO reading/writing jobs. CONSTITUTION:The new data is inputted to an accumulator 11 in synchronism with a first data synchronizing signal CLK 1, and the output of the accumulator 11 is stored in a line memory 12. Then the second new data is added with the old data stored in the memory 12 via an accumulator 11. This addition data is stored in the memory 12 synchronously with A11...Ann of the CLK 1. The addition operation in an addition part 1 of the line memory 12 for the accumulator 11 and the FIFO is stopped with a command of an MPU via an I/F part 34, when the addition frequency is integrated by a memory control counter 33 and the frequency reaches a prescribed level. Then a gate G121 and a gate G223 are closed and opened respectively and the addition data stored in a low-speed RAM 22 is read out by the MPU.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a repeat adder circuit that repeatedly adds a plurality of data, and an object of the present invention is to obtain a repeat adder circuit that has a particularly simple configuration, operates at high speed, and is inexpensive. do.

[Conventional technology]

Conventionally, this type of repetitive addition circuit has been shown in FIGS. 3 and 4. Figure 3 shows a circuit configuration diagram of a conventional adder circuit.
includes an accumulator (11) that sequentially accumulates new data inputted from one side and previously added and outputted data inputted from the other side, and a control unit (2) that controls the data outputted from the accumulator (11), which will be described later. ) is a high-speed static ram (
(hereinafter referred to as high-speed 5-RAM) (13) and the high-speed 5-RAM
Control unit (2) connected to the input/output side of RAM (13)
writing to high-speed 5-RAM (13) under the control of
Return to accumulator (11) and accumulator (
11) Gate G for controlling opening/closing of output to the outside from
(14), gate G2 (15), gate hG3 (16)
A control unit (2) for controlling access to the high-speed S-RAM (13) and opening/closing of the gates (14), (15), and (16) is connected to the gate G3 (
16) outputs the accumulated results of the accumulator (11).

The control unit (3) uses a data synchronization signal CLKI of a clock synchronized when new data is input to the accumulator (11), and a central processing unit (hereinafter referred to as CPU).
A read/write/reset signal S1 from (4) is input, and based on these signals, the read, write, and erase operations of the high-speed S-RAM (13) are controlled, and each of the gates (14) and (15) is controlled. ), (16), and an address generation circuit (31) that generates an address for the high-speed 5-RAM (13) based on the data synchronization signal CLKI and read/write/reset signal S. 32) and the address generation circuit (32)
) and the address signal A from the CPU (4), the high-speed S-R8M based on the select signal CI.
(13) A memory address selector (33) for selecting a memory address.

Next, the operation of the conventional iterative addition circuit will be explained based on the above configuration. First, when the first data string A-N is input as new data to the accumulator (11), a data synchronization signal CLKI synchronized with this new data is sent to the memory controller (31) of the control section (3) and the address generation circuit ( 32). The above memory controller (
Based on the control of 31), gate G, (14) opens, and new data passes through this gate G, (14) and is stored in a predetermined memory area of high-speed S-R8M (13>. Storage in the RAM (13) is performed under the control of an address generation circuit (32) and a memory address selector (33).

In addition, there is another conventional repetitive addition circuit shown in FIG. 4, which consists of a single accumulator (11) and a single accumulator (11)
1) is connected to the output side of the static ram (S-RA
RAM+ (13a) RAM2 (1
3b) and a gate G that controls the accumulation and output of the accumulator (11), (14a)-Gate 1-G
4 (14b) - Gate G2 (15a) - Gate c
5 (15b), K1-G3 (16a), and G1-C6 (t6b), and each of the dual RAMs and gates is connected to a "double accumulator" under the control of the control section (3). This configuration outputs the cumulative results of 11).

Another conventional circuit based on the above configuration includes an accumulator (1
1) Store the output from RAM+ (13a),
This stored old data and new data are added in the accumulator (11), and the addition result is stored in RAM2 (
13b). This R/MI (13a)
For RAM2 (13b) and RAM2 (13b), either read or write operation for one addition of the accumulator (11) can be performed in only one cycle, and takes about % of the time compared to when configured with a single memory. It will be possible to operate.

[Problems that the invention attempts to solve]

Since the conventional repeating addition circuit is configured as described above, the operating speed depends on the memory access time, so in order to operate at high speed, it is necessary to use a high-speed 5-RAM, and this high-speed 5-RAM Since it is expensive, it has been difficult to reduce the cost of the entire circuit.

Furthermore, since other conventional repeating adder circuits are configured as described above, the circuit configuration of the memory and the gates connected to the input and output sections of this memory is complicated and large-scale, and the control operation is also complicated. We had the challenge of becoming.

This invention was made to solve the above problems,
It is an object of the present invention to obtain a repetitive adder circuit that is inexpensive and has a simplified circuit configuration without using an expensive high-speed S-It AM.

[Means to solve the problem]

The iterative addition circuit according to the present invention adds the new data to the previously input day data by the accumulator every time new data is input, and selects one of the series of data output from the accumulator. storing a series of data in a first-in, first-out storage means in a first-in, first-out manner in which an old data element inputted first is read first; inputting the output of the first-in, first-out storage means to an accumulating means;
The configuration is such that this input data and new data are added.

(Function) The first-in, first-out storage means of the present invention can be used to insert a data element at the beginning of a data element among the image processing methods developed for limited use in today's diversified memories. Reading and writing are performed sequentially using a first-in, first-out method that takes data from the end, thereby achieving high-speed operation with a simple configuration.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 shows a circuit configuration diagram of the iterative addition circuit according to the present embodiment, and in the figure, each time new data is input, the iterative addition circuit according to the embodiment Accumulator (11
), and the series of data is stored in the line memory (12) in a first-in, first-out manner in which the oldest data element inputted first among the series of data output from the accumulator (11) is read out first. an adder (1) that feeds back and inputs the output of the line memory (12) to the accumulator (11) and adds the input data and new data;
an addition result output section (2) that stores the output of the addition section (1) in a low-speed RAM (22) and outputs it to an external MPU (not shown); A control section (3) controls the output operation of the addition result output section (2).
).

The line memory (12) is primarily created as a memory for image processing, and is a memory that stores one line of video signals.
rst out) memory.

The addition result output section (2) includes a gate G (21) that controls the input of addition data to the addition section (1), and the gate G
A low-speed RAM (22) that stores the added data output through I (21), and a gate G that controls the output of the added data from the low-speed RAM (22) and the adder (1).
2 (23).

The control unit (3) sets a data synchronization signal CL synchronized with new data to 1, a transfer lock CLK2, and a switching signal G.
A first memory address selector (31) that generates a clock signal for the line memory (12) based on LK3, a repetitive synchronization signal TCKI, and a transfer start signal TCK.
a second memory address selector (32) that generates a reset signal for the line memory (12) based on the switching signal CLK3 and the switching signal CLK3; and a clock for each of the first and second memory address selectors (31) and (32). Outputs read/write signals and address signals to the low-speed RAM (22) based on signals/reset signals and control signals input via the MPU side I/F (34),
first and second memory address selectors (31);
The configuration includes a memory controller (33) that outputs a switching signal LCK3 to (32).

Next, the operation of this embodiment based on the above configuration will be explained based on FIGS. 1 and 2. First, the accumulator (11)
By setting all inputs to °゛0゛, line memory (12
) is released from storage. In this state, new data is input to the accumulator (11) in synchronization with the first data synchronization signal CLKI, and the output of this accumulator (11) is stored in the line memory (12). The storage in this line memory (12) is A1...Δ of the data synchronization signal CLKI in FIG. is repeated and ends. Input to the accumulator (11) is performed by latching new data with the data synchronization signal CLKI and inputting it to the accumulator (11).
1) The uncertain operation time is shortened. Further, since the line memory (12) usually has an address counter built-in, there is no need to provide a special external circuit.

Furthermore, the new data input for the second time and the old data stored in the line memory (12) are stored in the accumulator (
11), and this added data is stored in the line memory (12) in synchronization with A1□...Ann of the data synchronization signal CLK1. This line memory (12)
Normally, the D-RAM structure requires refreshing, but since the repeating adder itself periodically performs an operation of storing new data on the D-RAM, no special refresh operation is required. Therefore, the period of repeated addition must be shorter than the period of refresh operation.

The above accumulator (11) and line memory (12)
The addition operation in the addition unit (1) is stopped based on a command from the MPU through the I/F unit (34) when the number of additions is accumulated by the memory control counter (33) and reaches a predetermined set number of times. controlled.

When the addition operation of the adder (1) is completed, the controller (2)
) in the first and second memory address selectors (3
1), (32), the memory controller (33) outputs 3 to the switching signal LC, and the gate G, (21)
will be held. Switching of the first and second memory address selectors (31), (32) and gates G, (
21), the addition data stored in the line memory (12) is stored in the low-speed RAM (22).

The addition data stored in the low-speed RAM (22) is
The MPU reads the data by closing the gate G (21) and opening the gate G2 (23). Since the read operation of the low-speed RAM (22) is performed at a low speed under the control of the MPLI side, it is performed separately from the high-speed operation of the adder (1). Therefore,
The time required for data collection by the MPU is only the data read time. On the other hand, the time required for averaging is (
It is generally long, calculated as (period) x (number of times), and during this time the MPU can read and write data in the low-speed RAM (22) at low speed, making the interface with the MPU simple.

The repetitive addition circuit in this embodiment has a configuration that outputs the addition result to an external MPU as having an addition result output section (2) and a control section (3), but the averaging circuit of the digital oscilloscope and the digital It can also be configured as an averager or the like.

〔Effect of the invention〕

As described above, according to the present invention, since the addition data sequentially output by the accumulating means is stored in the first-in, first-out storage means in a first-in, first-out manner, first-in, first-out reading and
Writing can be performed sequentially, which has the effect of simplifying the circuit configuration and reducing costs by using an inexpensive memory.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a repeat adder circuit according to an embodiment of the present invention, FIG. 2 is a timing diagram of the relationship between new data, data synchronization signal, and repeat synchronization signal, and FIGS. 3 and 4 are diagrams of a conventional repeat adder circuit. Each circuit configuration diagram of the adder circuit is shown. (1)... Addition section (2)... Addition result output section (3
)...Control unit (11)...Accumulator (12
)...Line memory (21), (23)...
Gate (22): Low-speed RAM Note that the same reference numerals in the drawings indicate the same or equivalent parts.

Claims (1)

[Claims] an accumulator that adds the new data to the previously input old data each time new data is input; and an accumulator that adds the new data to the previously input old data; a first-in, first-out storage means for storing a series of data read out in a first-in, first-out manner; the output of the first-in, first-out storage means is input to an accumulating means, and the input data and new data are added. A repeating addition circuit featuring: