JPH0283739A - Interruption processing system for information processor - Google Patents

Abstract

PURPOSE:To attain a macrocode processing system having a high freedom degree by producing an instruction to a macrocode via an interruption produced during the execution of a macrocode. CONSTITUTION:When a specific instruction or event is detected at execution of a program of a software area, an MCRM flag 1 is set at 1 via a signal line 102 and the subsequent instructions are carried out in a macromode. In this case, an input line 105 of an adder 5 shows the contents of an MPFXR 2. The real addresses set at a RAM 3 are added together by the adder 5 and converted by a soft prefix conversion logic part 6. Then the absolute address of a main storage is outputted to a signal line 107. While the line 105 is set at 0 when the flag 1 is set at 0, and an output line 106 shows the contents themselves of the RAM 3. Thus a macrocode can be processed with a high freedom degree.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an interrupt processing method for an information processing device, and in particular, a main memory is divided into a hardware area and a software area,
The present invention relates to an interrupt processing method in an instruction execution procedure for processing a specific instruction stored in a hardware area.

[Conventional technology]

In conventional information processing devices, instructions are processed by microprograms stored in fixed logic circuits or control memory. There are some instructions that are used very infrequently, and instructions that are executed by extremely complex and diverse processing, but when trying to execute these instructions with a conventional information processing device, the fixed logic circuit becomes complicated, This results in an increase in control storage capacity and microprograms. In particular, if the complexity of the fixed logic circuit affects the performance of frequently used basic instructions, the processing device becomes extremely unbalanced in terms of price/performance ratio.

Conventionally, in order to improve this point, the main memory is divided into a hardware area and a software area, and the hardware area contains a sequence of multiple types of instruction execution procedures, and the rough 1~wear area contains a normal program. An information processing apparatus has been proposed in which a sequence of instruction execution procedures is stored and executed when a program issues a specific instruction or when a specific event occurs.

In such information processing devices, when a program issues a specific instruction or a specific event occurs, the program executes the program state word (PSW), general purpose register (GR), floating point register (FR), etc. After the necessary resources are saved as described above, a sequence of instruction execution procedures (hereinafter referred to as macro code) in the hardware area is executed.

The macro code is free to use the resources for processing, but must recover the resources when the macro code completes, except for those that the macro code should explicitly update. If no interrupt factor occurs during the execution of the macro code, the above recovery process may be performed only when the macro code is completed.
If a program interrupt factor or machine check interrupt factor occurs during macro code execution, resources must be recovered in the interrupt processing as well. Conventionally, these interrupt processes have been implemented using hardware or microprograms for each type of interrupt.

Incidentally, related information processing apparatuses of this type include, for example, Japanese Patent Application Laid-Open No. 56-21237 and Japanese Patent Application Laid-Open No. 56-12.
4.952 and the like.

[Problem to be solved by the invention]

2. In conventional information processing devices, all interrupt processing during macro code execution is realized by hardware or microprograms, resulting in a considerable increase in control storage capacity and microprograms. This would defeat the original purpose of the macro code, which was to reduce the amount of data.

Further, it is desirable that the macro code has a high degree of freedom, including interrupt processing, similar to programs in the software domain.

This is because if the function to be realized by macro code has multiple program interrupt sources, it is more flexible to hold the interrupt sources in macro code and take responsibility for the final interrupt processing. This is because it is possible to realize a macro code that is rich in information. Conventionally, this point has not been considered, and the microcode has not been used effectively.

An object of the present invention is to realize an interrupt processing power formula for providing macro code processing with a high degree of freedom without increasing control storage capacity or microprograms.

[Failure to solve the problem]

In order to achieve the above object, the present invention divides the main memory into a software area and a hardware area, the rough 1-ware area stores programs, and the hardware area stores programs for processing specific instructions or events. For example, when a program in the software area is being executed in an information processing device that stores a sequence of instruction execution procedures (macro codes) to be executed when a
I+, when executing a sequence of instruction execution procedures in the hardware area, for example, L(i). An identifier indicating I+ and a first interrupt procedure for an interrupt factor that occurs during execution of a program in the software area. and a second interrupt procedure for an interrupt factor that occurs during execution of a sequence of instruction execution procedures in the hardware area, and the identifier is r.
r For an interrupt factor that occurs when OI+, perform the interrupt processing using the first interrupt procedure, and for an interrupt factor that occurs when the identifier is "1", use the second interrupt procedure. It is characterized by

[For production]

When an interrupt factor occurs during macro code execution in the hardware area, the information processing device stores the interrupt in a part of the hardware area and processes the interrupt on the macro code side according to the interrupt procedure (the water interrupt procedure is written in macro code). I do. This is recognized by the program in the software area as just a part of the execution of the macro code, and does not generate an interrupt for the program in the software area. Therefore, interrupts that occur during the execution of the macro code are solely the responsibility of the macro code. It becomes possible to perform interrupt processing at the same time. Furthermore, after the interrupt processing by the macro code is completed, the processing result of the macro code is reported to the program in the software area by the macro code.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing the division of the main memory. The main memory 10 has a hardware area (H8A) 11 and a software area (H8A) 11.
SA) It is divided into 12. The hardware area 11 includes a sequence of instruction execution procedures for processing specific instructions stored in the software area 12 and a sequence of instruction execution procedures for processing to be performed when a specific event occurs (hereinafter referred to as , macro code), etc. are stored. Furthermore, this hardware area 11 includes a macro prefix area (MPFX) for holding information regarding interrupts that occur during macro code execution. MPFX
In the case of a multiprocessor configuration in which one main memory is shared by a plurality of processing devices, as many as the number of processing devices are prepared. MPF when rowing consists of two processing devices
XO and MPFXI are shown.

The software area 12 has a soft prefix area (SPFX) that holds information regarding an interrupt that occurs during the execution of a program stored in the software area or an interrupt that occurs during the execution of the macro code.

SPF) Similar to IMPFX, as many processing units as there are are prepared, and two cases, SPFXO and 5PFXI, are shown here.

FIG. 1 shows an embodiment of interrupt processing means according to the present invention. The macro mode (MCRM) flag 1 is a flip-flop that is set to "1" by the signal line 101 during execution of the macro code in the hardware area 11 of the main memory 10. Macro Prefix Register (MPF)
XR)2 is a register that holds the start address of the macro prefix area (MPFX) assigned to the processing device through the signal line 103. The real address register (RAR) 3 is a register that holds the real address of the main memory to be accessed by the processing device via the signal line 104. Although omitted in FIG. 1, the signal line 101 is connected to the instruction control unit, and the signal lines 103 and 104 are connected to the storage control unit.

As the concept of interrupt processing is shown in Figure 3, the current program status word (current psw) is stored in the old PSW storage area of the prefix area in the main memory, and the new PSW prepared in advance is stored in the new PSW storage area. This is the process of setting the current PSW. Through this process, the execution of the program indicated by the current PSW is interrupted, and the program indicated by the new PSW is newly executed. In the present invention, if the interrupt processing is performed in the macro prefix area during macro code execution, the interrupt will be performed on the macro code, and if the interrupt processing is performed in the soft prefix area. , the interrupt will be made to the program.

Next, interrupt processing during execution of the macro mode, which is a feature of the present invention, will be explained with reference to FIG.

When a specific instruction or a specific event is detected in the execution of a program in the software area, M, C
The RM flag 1 is set to 1'' by the signal line 102, indicating that the subsequent instruction execution will be executed under the macro mode.When this MCRMl is "1", the signal line 102
becomes “1”, and the input line 105 of the adder 5 is MPFXR.
2 (start address of MPFX). RAR3
The real address set in is sent to input line 10 by adder 5.
5 and it passes through signal 106 and is added to the rough 1
- After performing soft prefix conversion in the prefix conversion logic section 6, the main memory absolute address is outputted to the signal 107. In other words, when a real address indicating the storage area of the old PSW, new PSW, etc. in the prefix area is set in RAR3, the real address is finally stored in the macro prefix area (MPFXO or MPFXO in Figure 2).
I) is converted into an absolute address indicating the storage area of the old PSW, new PSW, etc.

On the other hand, while the software area program is being executed in software 1, M and C
When RMl is HOIT, input line 1.05 of adder 5 is “
O'', and the output line 106 of the adder 5 becomes the contents of RAR3 itself. Therefore, when a real address similar to the above is set in RAR3, the real address is converted to a real address indicating the soft prefix area.

〔Effect of the invention〕

As described above, according to the present invention, an interrupt that occurs during execution of a macro code causes an interrupt to the macro code, so that macro code processing with a high degree of freedom can be provided. In addition, since the hardware switches the access address when accessing the software prefix area in the rough 1 to wear area or the macro prefix area in the hardware area using the macro flag, interrupt processing can be performed without increasing the size of the interrupt processing microprogram. becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the interrupt processing means according to the present invention, and FIG. 2 shows the hardware area of the main memory and rough 1 to
FIG. 3, which is a division diagram of the wear area, is a diagram representing the concept of interrupt processing. 1.Flip-flop for macro mode flag, 2..
Macro prefix register, 3... Real address register, 4... AND'y'-to, 5... Adder, 6... Soft prefix conversion logic unit, 10
...Main storage device, 11.・Hardware area,
12...Software area.

Claims (2)

[Claims] (1) Divide the main memory into a software area and a hardware area, with the software area containing programs and the hardware area executing instructions that are executed when processing specific instructions or when specific events occur. In an information processing device that stores a sequence of procedures, a first state is entered when a program in the software area is executed, and a second state is entered when a sequence of instruction execution procedures in the hardware area is executed. a first interrupt procedure for an interrupt cause that occurs during execution of a program in the software area; and a second interrupt procedure for an interrupt cause that occurs during execution of a sequence of instruction execution procedures in the hardware area; The first interrupt procedure is used for an interrupt factor that occurs when the identifier is in a first state, and the second interrupt procedure is used for an interrupt factor that occurs when the identifier is in a second state. An interrupt processing method characterized by performing interrupt processing. (2) A first interrupt procedure for an interrupt cause that occurs during execution of a program in the software area is provided in the software area, and a second interrupt procedure for an interrupt cause that occurs during execution of a sequence of instruction execution procedures in the hardware area. 2. The interrupt processing method according to claim 1, wherein the interrupt procedure is provided in a hardware area.