JPH028234U - - Google Patents
Info
- Publication number
- JPH028234U JPH028234U JP8590488U JP8590488U JPH028234U JP H028234 U JPH028234 U JP H028234U JP 8590488 U JP8590488 U JP 8590488U JP 8590488 U JP8590488 U JP 8590488U JP H028234 U JPH028234 U JP H028234U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- pll
- sampling
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005070 sampling Methods 0.000 claims description 7
- 238000001514 detection method Methods 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 claims 2
- 239000000284 extract Substances 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第1図及び第2図はこの考案に係るPLL回路
の実施例を示し、第1図はブロツク図、第2図は
他の実施例を示したブロツク図である。第3図は
従来のPLL回路のブロツク図である。
主な番号の説明、2:PLL回路、3:位相比
較回路、4:ローパスフイルタ(LPF)、5:
電圧制御発振回路(VCO)、10:データ検出
回路、11,21:スイツチ、12:LPF伝達
関数切換回路、13:コンパレータ、14,24
:基準電圧発生回路、20:サンプリングパルス
発生回路、23:サンプルホールド回路。
1 and 2 show an embodiment of a PLL circuit according to this invention, with FIG. 1 being a block diagram and FIG. 2 being a block diagram showing another embodiment. FIG. 3 is a block diagram of a conventional PLL circuit. Explanation of main numbers, 2: PLL circuit, 3: Phase comparison circuit, 4: Low pass filter (LPF), 5:
Voltage controlled oscillator circuit (VCO), 10: Data detection circuit, 11, 21: Switch, 12: LPF transfer function switching circuit, 13: Comparator, 14, 24
: Reference voltage generation circuit, 20: Sampling pulse generation circuit, 23: Sample hold circuit.
Claims (1)
クロツク信号を抽出するPLL回路において、 再生信号の有無を検出する検出回路と、この検
出回路の出力信号で制御するスイツチと、基準電
圧発生部とコンパレータより構成した上記PLL
回路のローパスフイルタの伝達関係切換回路とを
設け、再生信号の無い時、上記スイツチを介して
入力するVCO制御電圧と上記基準電圧とを比較
する上記コンパレータの出力信号でローパスフイ
ルタの伝達関係の電圧を設定するように構成した
ことを特徴とするPLL回路。 2 再生信号が入力されない時にサンプリングパ
ルスを発生するサンプリングパルス発生回路と、
このサンプリングパルス発生回路の出力信号で制
御するスイツチと、基準電圧発生部を内蔵したサ
ンプリングホールド回路とを設け、再生信号の無
い時、上記スイツチを介して入力するVCO制御
電圧を上記サンプリングホールド回路にサンプル
ホールドし、このサンプリングホールド回路の出
力信号を上記PLL回路のローパスフイルタの入
力側に帰還するように構成したことを特徴とする
請求項1記載のPLL回路。[Claims for Utility Model Registration] 1. In a PLL circuit that extracts a synchronous clock signal from a playback signal recorded on a recording medium, a detection circuit that detects the presence or absence of a playback signal, and control using the output signal of this detection circuit. The above PLL consists of a switch, a reference voltage generator, and a comparator.
A low-pass filter transmission relationship switching circuit is provided in the circuit, and when there is no reproduction signal, the output signal of the comparator compares the VCO control voltage input through the switch with the reference voltage, and the low-pass filter transmission relationship voltage is determined. A PLL circuit characterized in that it is configured to set. 2. A sampling pulse generation circuit that generates a sampling pulse when no reproduction signal is input;
A switch controlled by the output signal of this sampling pulse generation circuit and a sampling hold circuit with a built-in reference voltage generation section are provided, and when there is no reproduction signal, the VCO control voltage input via the switch is applied to the sampling hold circuit. 2. The PLL circuit according to claim 1, wherein the PLL circuit is configured to sample and hold and feed back the output signal of the sampling and hold circuit to the input side of a low-pass filter of the PLL circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988085904U JPH0741217Y2 (en) | 1988-06-30 | 1988-06-30 | PLL circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988085904U JPH0741217Y2 (en) | 1988-06-30 | 1988-06-30 | PLL circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH028234U true JPH028234U (en) | 1990-01-19 |
JPH0741217Y2 JPH0741217Y2 (en) | 1995-09-20 |
Family
ID=31310556
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1988085904U Expired - Lifetime JPH0741217Y2 (en) | 1988-06-30 | 1988-06-30 | PLL circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0741217Y2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5365449A (en) * | 1976-11-22 | 1978-06-10 | Teishichi Hayashi | Device for warp feeding into circular knitting machine |
JPS5432340U (en) * | 1977-08-05 | 1979-03-02 | ||
JP2007114165A (en) * | 2005-10-24 | 2007-05-10 | Nippon Reliance Kk | Device and method for detecting position of moving object |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57176844A (en) * | 1981-04-23 | 1982-10-30 | Mitsubishi Electric Corp | Phase synchronizing oscillator |
JPS57195311A (en) * | 1981-05-26 | 1982-12-01 | Victor Co Of Japan Ltd | Clock regenerating circuit |
JPS58131820A (en) * | 1982-01-29 | 1983-08-05 | Nec Corp | Phase locked loop circuit |
JPS6157122A (en) * | 1984-08-28 | 1986-03-24 | Nec Corp | Pll circuit |
JPS61189019A (en) * | 1985-02-16 | 1986-08-22 | Nec Corp | Phase locked oscillating circuit |
-
1988
- 1988-06-30 JP JP1988085904U patent/JPH0741217Y2/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57176844A (en) * | 1981-04-23 | 1982-10-30 | Mitsubishi Electric Corp | Phase synchronizing oscillator |
JPS57195311A (en) * | 1981-05-26 | 1982-12-01 | Victor Co Of Japan Ltd | Clock regenerating circuit |
JPS58131820A (en) * | 1982-01-29 | 1983-08-05 | Nec Corp | Phase locked loop circuit |
JPS6157122A (en) * | 1984-08-28 | 1986-03-24 | Nec Corp | Pll circuit |
JPS61189019A (en) * | 1985-02-16 | 1986-08-22 | Nec Corp | Phase locked oscillating circuit |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5365449A (en) * | 1976-11-22 | 1978-06-10 | Teishichi Hayashi | Device for warp feeding into circular knitting machine |
JPS5616215B2 (en) * | 1976-11-22 | 1981-04-15 | ||
JPS5432340U (en) * | 1977-08-05 | 1979-03-02 | ||
JPS5731180Y2 (en) * | 1977-08-05 | 1982-07-08 | ||
JP2007114165A (en) * | 2005-10-24 | 2007-05-10 | Nippon Reliance Kk | Device and method for detecting position of moving object |
Also Published As
Publication number | Publication date |
---|---|
JPH0741217Y2 (en) | 1995-09-20 |
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