JPH0282048U - - Google Patents

Info

Publication number
JPH0282048U
JPH0282048U JP16140788U JP16140788U JPH0282048U JP H0282048 U JPH0282048 U JP H0282048U JP 16140788 U JP16140788 U JP 16140788U JP 16140788 U JP16140788 U JP 16140788U JP H0282048 U JPH0282048 U JP H0282048U
Authority
JP
Japan
Prior art keywords
pin
semiconductor integrated
integrated circuit
circuit package
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16140788U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16140788U priority Critical patent/JPH0282048U/ja
Publication of JPH0282048U publication Critical patent/JPH0282048U/ja
Pending legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案が適用されるPGA構造の半導
体集積回路パツケージの斜視図、第2図は本考案
の一実施例におけるピンの拡大断面図、第3図は
ピンの下面図、第4図は本考案の他の実施例のピ
ンの拡大断面図、第5図は従来のピンの一部の側
面図である。 1……パツケージ本体、2……ピン、3……凸
条、4……スプリング、5……突起。
Fig. 1 is a perspective view of a semiconductor integrated circuit package with a PGA structure to which the present invention is applied, Fig. 2 is an enlarged sectional view of a pin in an embodiment of the present invention, Fig. 3 is a bottom view of the pin, and Fig. 4 5 is an enlarged sectional view of a pin according to another embodiment of the present invention, and FIG. 5 is a side view of a portion of a conventional pin. 1...Package body, 2...Pin, 3...Protrusion, 4...Spring, 5...Protrusion.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] パツケージ本体から突出されたピンをプリント
回路基板に半田付けして実装を行う半導体集積回
路パツケージにおいて、前記ピンを先端が開口さ
れた筒状に形成し、かつこのピンの内部にはピン
内に挿入されたチエツク用プローブに電気接触さ
れる接触部を形成したことを特徴とする半導体集
積回路パツケージ。
In a semiconductor integrated circuit package that is mounted by soldering a pin protruding from the package body to a printed circuit board, the pin is formed into a cylindrical shape with an open end, and the pin is inserted into the pin. A semiconductor integrated circuit package characterized in that a contact portion is formed to make electrical contact with a checked probe.
JP16140788U 1988-12-13 1988-12-13 Pending JPH0282048U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16140788U JPH0282048U (en) 1988-12-13 1988-12-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16140788U JPH0282048U (en) 1988-12-13 1988-12-13

Publications (1)

Publication Number Publication Date
JPH0282048U true JPH0282048U (en) 1990-06-25

Family

ID=31444314

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16140788U Pending JPH0282048U (en) 1988-12-13 1988-12-13

Country Status (1)

Country Link
JP (1) JPH0282048U (en)

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